Model build in the presence of a non-binding reference

ABSTRACT

One or more hardware description language (HDL) files describe a plurality of hierarchically arranged design entities defining a digital design to be simulated and a plurality of configuration entities not belonging to the digital design that logically control settings of a plurality of configuration latches in the digital design. The HDL file(s) are compiled to obtain a simulation executable model of the digital design and an associated configuration database. The compiling includes parsing a configuration statement that specifies an association between an instance of a configuration entity and a specified configuration latch, determining whether or not the specified configuration latch is described in the HDL file(s), and if not, creating an indication in the configuration database that the instance of the configuration latch had a specified association to a configuration latch to which it failed to bind.

The present application is related to U.S. patent application Ser. Nos. 10/902,628 and ______ (Docket No. AUS920060575US1), which are incorporated herein by reference in their entireties.

BACKGROUND OF THE INVENTION

1. Background of the Invention

2. Technical Field

The present invention relates in general to designing, simulating and configuring digital devices, modules and systems, and in particular, to computer-aided design, simulation, and configuration of digital devices, modules and systems described by a hardware description language (HDL) model.

3. Description of the Related Art

In a typical digital design process, verifying the logical correctness of a digital design and debugging the design (if necessary) are important steps of the design process performed prior to developing a circuit layout. Although it is certainly possible to test a digital design by actually building the digital design, digital designs, particularly those implemented by integrated circuitry, are typically verified and debugged by simulating the digital design on a computer, due in part to the time and expense required for integrated circuit fabrication.

In a typical automated design process, a circuit designer enters into an electronic computer-aided design (ECAD) system a high-level description of the digital design to be simulated utilizing a hardware description language (HDL), such as VHDL, thus producing a digital representation of the various circuit blocks and their interconnections. In the digital representation, the overall circuit design is frequently divided into smaller parts, hereinafter referred to as design entities, which are individually designed, often by different designers, and then combined in a hierarchical manner to create an overall model. This hierarchical design technique is very useful in managing the enormous complexity of the overall design and facilitates error detection during simulation.

The ECAD system compiles the digital representation of the design into a simulation model having a format best suited for simulation. A simulator then exercises the simulation model to detect logical errors in the digital design.

A simulator is typically a software tool that operates on the simulation model by applying a list of input stimuli representing inputs of the digital system. The simulator generates a numerical representation of the response of the circuit to the input stimuli, which response may then either be viewed on the display screen as a list of values or further interpreted, often by a separate software program, and presented on the display screen in graphical form. The simulator may be run either on a general-purpose computer or on another piece of electronic apparatus specially designed for simulation. Simulators that run entirely in software on a general-purpose computer are referred to as “software simulators,” and simulators that run with the assistance of specially designed electronic apparatus are referred to as “hardware simulators.”

As digital designs have become increasingly complex, digital designs are commonly simulated at several levels of abstraction, for example, at functional, logical and circuit levels. At the functional level, system operation is described in terms of a sequence of transactions between registers, adders, memories and other functional units. Simulation at the functional level is utilized to verify the high-level design of digital systems. At the logical level, a digital system is described in terms of logic elements such as logic gates and flip-flops. Simulation at the logical level is utilized to verify the correctness of the logic design. At the circuit level, each logic gate is described in terms of its circuit components such as transistors, impedances, capacitances, and other such devices. Simulation at the circuit level provides detailed information about voltage levels and switching speeds.

In order to verify the results of any given simulation run, custom-developed programs written in high-level languages such as C or C++, referred to as a reference model, are written to process input stimuli (also referred to as test vectors) to produce expected results of the simulation run. The test vector is then run against the simulation execution model by the simulator. The results of the simulation run are then compared to the results predicted by the reference model to detect discrepancies, which are flagged as errors. Such a simulation check is known in the verification art as an “end-to-end” check.

In modern data processing systems, especially large server-class computer systems, the number of latches that must be loaded to configure the system for operation (or simulation) is increasing dramatically. One reason for the increase in configuration latches is that many chips are being designed to support multiple different configurations and operating modes in order to improve manufacturer profit margins and simplify system design. For example, memory controllers commonly require substantial configuration information to properly interface memory cards of different types, sizes, and operating frequencies.

A second reason for the increase in configuration latches is the ever-increasing transistor budget within processors and other integrated circuit chips. Often the additional transistors available within the next generation of chips are devoted to replicated copies of existing functional units in order to improve fault tolerance and parallelism. However, because transmission latency via intra-chip wiring is not decreasing proportionally to the increase in the operating frequency of functional logic, it is generally viewed as undesirable to centralize configuration latches for all similar functional units. Consequently, even though all instances of a replicated functional unit are frequently identically configured, each instance tends to be designed with its own copy of the configuration latches. Thus, configuring an operating parameter having only a few valid values (e.g., the ratio between the bus clock frequency and processor clock frequency) may involve setting hundreds of configuration latches in a processor chip.

Conventionally, configuration latches and their permitted ranges of values have been specified by error-prone paper documentation that is tedious to create and maintain. Compounding the difficulty in maintaining accurate configuration documentation and the effort required to set configuration latches is the fact that different constituencies within a single company (e.g., a functional simulation team, a laboratory debug team, and one or more customer firmware teams) often separately develop configuration software from the configuration documentation. As the configuration software is separately developed by each constituency, each team may introduce its own errors and employ its own terminology and naming conventions. Consequently, the configuration software developed by the different teams is not compatible and cannot easily be shared between the different teams.

SUMMARY OF THE INVENTION

In at least one embodiment, one or more hardware description language (HDL) files describe a plurality of hierarchically arranged design entities defining a digital design to be simulated and a plurality of configuration entities not belonging to the digital design that logically control settings of a plurality of configuration latches in the digital design. The HDL file(s) are compiled to obtain a simulation executable model of the digital design and an associated configuration database. The compiling includes parsing a configuration statement that specifies an association between an instance of a configuration entity and a specified configuration latch, determining whether or not the specified configuration latch is described in the HDL file(s), and if not, creating an indication in the configuration database that the instance of the configuration latch had a specified association to a configuration latch to which it failed to bind.

All objects, features, and advantages of the present invention will become apparent in the following detailed written description.

BRIEF DESCRIPTION OF THE DRAWINGS

The novel features believed characteristic of the invention are set forth in the appended claims. However, the invention, as well as a preferred mode of use, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:

FIG. 1 is a high level block diagram of a data processing system that may be utilized to implement the present invention;

FIG. 2 illustrates an exemplary simulation model of a digital design including a plurality of hierarchically arranged design entities;

FIG. 3A is a diagrammatic representation of an LDial primitive in accordance with the present invention

FIG. 3B depicts an exemplary digital design including a plurality of hierarchically arranged design entities in which LDials are instantiated in accordance with the present invention;

FIG. 3C illustrates an exemplary digital design including a plurality of hierarchically arranged design entities in which an LDial is employed to configure signal states at multiple different levels of the design hierarchy;

FIG. 4A is a diagrammatic representation of an IDial primitive in accordance with the present invention;

FIG. 4B is a diagrammatic representation of an IDial primitive having a split output in accordance with the present invention;

FIG. 5A is a diagrammatic representation of a CDial primitive employed to control other Dials in accordance with the present invention;

FIG. 5B depicts an exemplary digital design including a plurality of hierarchically arranged design entities in which a CDial is employed to control lower-level Dials utilized to configure signal states;

FIG. 6A depicts a diagrammatic representation of a Dial group;

FIG. 6B illustrates an exemplary simulation model including Dials grouped in multiple hierarchically arranged Dial groups;

FIG. 7 is a high level flow diagram of a model build process utilized to produce a simulation executable model and associated simulation configuration database in accordance with the present invention;

FIG. 8 depicts an exemplary embodiment of a simulation configuration database in accordance with the present invention;

FIGS. 9A-9B together form a high level logical flowchart of an exemplary method by which a configuration compiler parses each reference to a signal or Dial instance within a configuration specification statement in accordance with a preferred embodiment of the present invention;

FIG. 10 is a block diagram depicting the contents of volatile system memory during a simulation run of a simulation model in accordance with the present invention;

FIG. 11 is a high level logical flowchart of an exemplary method of locating one or more Dial instance data structure (DIDS) in a configuration database that are identified by a instance qualifier and dialname qualifier supplied in an API call;

FIG. 12A is a high level logical flowchart of an illustrative method of reading a Dial instance in an interactive mode during simulation of a digital design in accordance with the present invention;

FIG. 12B is a high level logical flowchart of an exemplary method of reading a Dial group instance in an interactive mode during simulation of a digital design in accordance with the present invention;

FIG. 13A is a high level logical flowchart of an illustrative method of setting a Dial instance in an interactive mode during simulation of a digital design in accordance with the present invention;

FIG. 13B is a high level logical flowchart of an exemplary method of setting a Dial group instance in an interactive mode during simulation of a digital design in accordance with the present invention;

FIG. 14A is a high level logical flowchart of an illustrative method of setting a Dial instance or Dial group instance in a batch mode during simulation of a digital design in accordance with the present invention; and

FIG. 14B is a more detailed flowchart of an end_phase API called within the process shown in FIG. 14A.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENT

With reference now to the figures, and in particular with reference to FIG. 1, there is depicted an exemplary embodiment of a data processing system in accordance with the present invention. The depicted embodiment can be realized, for example, as a workstation, server, or mainframe computer.

As illustrated, data processing system 6 includes one or more processing nodes 8 a-8 n, which, if more than one processing node 8 is implemented, are interconnected for communication by node interconnect 22 and respective node controllers 20. Processing nodes 8 a-8 n may each include one or more processors 10, a local interconnect 16, and a system memory 18 that is accessed via a memory controller 17. In addition to the registers, instruction flow logic and execution units utilized to execute program instructions, which are generally designated as processor core 12, each of processors 10 a-10 m also includes an on-chip cache hierarchy 14 that is utilized to stage data to the associated processor core 12 from system memories 18.

Local interconnect 16, which is governed by arbiter 24, is coupled, via mezzanine bus bridge 26, to a mezzanine bus 30. Mezzanine bus bridge 26 provides both a low latency path through which processors 10 may directly access devices among I/O devices 32 and storage devices 34 that are mapped to bus memory and/or I/O address spaces and a high bandwidth path through which I/O devices 32 and storage devices 34 may access system memory 18. I/O devices 32 may include, for example, a display device, a keyboard, a graphical pointer, and serial and parallel ports for connection to external networks or attached devices. Storage devices 34 may include, for example, optical or magnetic disks and/or flash memory that provide non-volatile storage for operating system, middleware and application software. In the present embodiment, such application software includes an ECAD system 35, which can be utilized to develop, verify and simulate a digital circuit design in accordance with the methods and systems of the present invention.

Simulated digital circuit design models created utilizing ECAD system 35 are comprised of at least one, and usually many, sub-units referred to hereinafter as design entities, which are described in detail in U.S. patent application Ser. No. 10/902,628 incorporated by reference above. By instantiating one or more design entities within one or more other design entities, a hierarchical description of an overall design is achieved. For example, a microprocessor may contain multiple instances of an identical functional unit. As such, the microprocessor itself will often be modeled as a single design entity. Within the microprocessor entity, multiple instantiations of any duplicated functional entities will be present. Each design entity is specified by one or more HDL files that contain the information necessary to describe the design entity. Although not required by the present invention, it will hereafter be assumed for ease of understanding that each design entity is specified by a respective HDL file.

With reference now to FIG. 2, there is illustrated a diagrammatic representation of an exemplary simulation model 300 that may be employed by ECAD system 35 to represent a digital design (e.g., an integrated circuit chip or a computer system) in a preferred embodiment of the present invention. For visual simplicity and clarity, the ports and signals interconnecting the design entities within simulation model 300 have not been explicitly shown.

Simulation model 300 includes a number of hierarchically arranged design entities. As within any simulation model, simulation model 300 includes one and only one “top-level entity” encompassing all other entities within simulation model 300. That is to say, top-level entity 302 instantiates, either directly or indirectly, all descendant entities within the digital design. Specifically, top-level entity 302 directly instantiates (i.e., is the direct ancestor of) two instances, 304 a and 304 b, of the same FiXed-point execution Unit (FXU) entity 304 and a single instance of a Floating Point Unit (FPU) entity 314. FXU entity instances 304, having instantiation names FXU0 and FXU1, respectively, in turn instantiate additional design entities, including multiple instantiations of entity A 306 having instantiation names A0 and A1, respectively.

Each instantiation of a design entity has an associated description that contains an entity name and an instantiation name, which must be unique among all descendants of the direct ancestor entity, if any. For example, top-level entity 302 has a description 320 including an entity name 322 (i.e., the “TOP” preceding the colon) and also includes an instantiation name 324 (i.e., the “TOP” following the colon). Within an entity description, it is common for the entity name to match the instantiation name when only one instance of that particular entity is instantiated within the ancestor entity. For example, single instances of entity B 310 and entity C 312 instantiated within each of FXU entity instantiations 304 a and 304 b have matching entity and instantiation names. However, this naming convention is not required by the present invention as shown by FPU entity 314 (i.e., the instantiation name is FPU0, while the entity name is FPU).

The nesting of entities within other entities in a digital design can continue to an arbitrary level of complexity, provided that all entities instantiated, whether singly or multiply, have unique entity names and the instantiation names of all descendant entities within any direct ancestor entity are unique with respect to one another.

Associated with each design entity instantiation is a so called “instantiation identifier”. The instantiation identifier for a given instantiation is a string including the enclosing entity instantiation names proceeding from the top-level entity instantiation name. For example, the design instantiation identifier of instantiation 312 a of entity C 312 within instantiation 304 a of FXU entity 304 is “TOP.FXU0.B.C”. This instantiation identifier serves to uniquely identify each instantiation within a simulation model.

As discussed above, a digital design, whether realized utilizing physical integrated circuitry or as a software model such as simulation model 300, typically includes configuration latches utilized to configure the digital design for proper operation. In contrast to prior art design methodologies, which employ stand-alone configuration software created after a design is realized to load values into the configuration latches, preferred embodiments utilize a configuration specification language that permits a digital designer to specify configuration values for signals as a natural part of the design process. In particular, the configuration specification language of the present invention permits a design configuration to be specified utilizing statements either embedded in one or more HDL files specifying the digital design (as illustrated and described with reference to FIG. 4A of U.S. patent application Ser. No. 10/902,628) or in one or more external configuration files referenced by the one or more HDL files specifying the digital design (as depicted and described with reference to FIG. 4B of U.S. patent application Ser. No. 10/902,628).

As discussed further below with reference to FIG. 7, configuration specification statements, whether embedded within an HDL file or collected in one or more configuration files 414, are processed by a compiler together with the associated HDL files. In accordance with a preferred embodiment of the present invention, configuration specification statements facilitate configuration of configuration latches within a digital design by instantiating one or more instances of a configuration entity referred to herein generically as a “Dial.” A Dial's function is to map between an input value and one or more output values. In general, such output values ultimately directly or indirectly specify configuration values of configuration latches. Each Dial is associated with a particular design entity in the digital design, which by convention is the design entity specified by the HDL source file containing the configuration specification statement or configuration file reference statement that causes the Dial to be instantiated. Consequently, by virtue of their association with particular design entities, which all have unique instantiation identifiers, Dials within a digital design can be uniquely identified as long as unique Dial names are employed within any given design entity. As will become apparent, many different types of Dials can be defined, beginning with a Latch Dial (or “LDial”).

Referring now to FIG. 3A, there is depicted a representation of an exemplary LDial 500. In this particular example, LDial 500, which has the name “bus ratio”, is utilized to specify values for configuration latches in a digital design in accordance with an enumerated input value representing a selected ratio between a component clock frequency and bus clock frequency.

As illustrated, LDial 500, like all Dials, logically has a single input 502, one or more outputs 504, and a mapping table 503 that maps each input value to a respective associated output value for each output 504. That is, mapping table 503 specifies a one-to-one mapping between each of one or more unique input values and a respective associated unique output value. Because the function of an LDial is to specify the legal values of configuration latches, each output 504 of LDial 500 logically controls the value loaded into a respective configuration latch 505. To prevent conflicting configurations, it is preferred that each configuration latch 505 is directly specified by one and only one Dial of any type that is capable of setting the configuration latch 505.

At input 502, LDial 500 receives an enumerated input value (i.e., a string) among a set of legal values including “2:1”, “3:1” and “4:1”. The enumerated input value can be provided directly by software (e.g., by a software simulator or service processor firmware) or can be provided by the output of another Dial, as discussed further below with respect to FIG. 5A. For each enumerated input value, the mapping table 503 of LDial 500 indicates a selected binary value (i.e., “0” or “1”) for each configuration latch 505.

With reference now to FIG. 3B, there is illustrated a diagrammatic representation of a simulation model logically including Dials. Simulation model 300′ of FIG. 3B, which as indicated by prime notation includes the same design entities arranged in the same hierarchical relation as simulation model 300 of FIG. 2, illustrates two properties of Dials, namely, replication and scope.

Replication is a process by which a Dial that is specified in or referenced by an HDL file of a design entity is automatically instantiated each time that the associated design entity is instantiated. Replication advantageously reduces the amount of data entry a designer is required to perform to create multiple identical instances of a Dial. For example, in order to instantiate the six instances of LDials illustrated in FIG. 3B, the designer need only code two LDial configuration specification statements. That is, the designer codes a first LDial configuration specification statement (or configuration file reference statement pointing to an associated configuration file) into the HDL file of design entity A 306 in order to automatically instantiate LDials 506 a 0, 506 a 1, 506 b 0 and 506 b 1 within entity A instantiations 306 a 0, 306 a 1, 306 b 0 and 306 b 1, respectively. The designer codes a second LDial configuration specification statement (or configuration file reference statement pointing to an associated configuration file) into the HDL file of design entity FXU 304 in order to automatically instantiate LDials 510 a and 510 b within FXU entity instantiations 304 a and 304 b, respectively. The multiple instances of the LDials are then created automatically as the associated design entities are replicated by the compiler. Replication of Dials within a digital design can thus significantly reduce the input burden on the designer as compared to prior art methodologies in which the designer had to individually enumerate in the configuration software each configuration latch value by hand. It should be noted that the property of replication does not necessarily require all instances of a Dial to generate the same output values; different instances of the same Dial can be set to generate different outputs by providing them different inputs.

The “scope” of a Dial is defined herein as a set of entities including the design entity with which the Dial is associated (e.g., the design entity specified by the HDL source file containing the configuration specification statement or configuration file reference statement that causes the Dial to be instantiated) and any design entity contained within the associated design entity (i.e., the associated design entity and its descendents). Thus, a Dial is not constrained to operate at the level of the design hierarchy at which it is instantiated, but can also specify configuration latches at least at any lower level of the design hierarchy within its scope. For example, LDials 510 a and 510 b, even though associated with FXU entity instantiations 304 a and 304 b, respectively, can specify configuration latches within entity C instantiations 312 a and 312 b, respectively.

FIG. 3B illustrates another important property of LDials (and other Dials that directly specify configuration latches). In particular, as shown diagrammatically in FIG. 3B, designers, who are accustomed to specifying signals in HDL files, are permitted in a configuration specification statement to specify signal states set by a Dial rather than values to be loaded into an “upstream” configuration latch that determines the signal state. Thus, in specifying LDial 506, the designer can specify possible signal states for a signal 514 set by a configuration latch 512. Similarly, in specifying LDial 510, the designer can specify possible signal states for signal 522 set by configuration latch 520. The ability to specify signal states rather than latch values not only coincides with designers' customary manner of thinking about a digital design, but also reduces possible errors introduced by the presence of inverters between the configuration latch 512, 520 and the signal of interest 514, 522, as discussed further below.

Referring now to FIG. 3C, there is depicted another diagrammatic representation of a simulation model including an LDial. As indicated by prime notation, simulation model 300″ of FIG. 3C includes the same design entities arranged in the same hierarchical relation as simulation model 300 of FIG. 2.

As shown, simulation model 300″ of FIG. 3C includes an LDial 524 associated with top-level design entity 302. LDial 524 specifies the signal states of each signal sig1 514, which is determined by a respective configuration latch 512, the signal states of each signal sig2 522, which is determined by a respective configuration latch 520, the signal state of signal sig4 532, which is determined by configuration latch 530, and the signal state of signal sig3 536, which is determined by configuration latch 534. Thus, LDial 524 configures the signal states of numerous different signals, which are all instantiated at or below the hierarchy level of LDial 524 (which is the top level).

As discussed above, LDial 524 can be instantiated within top-level entity 302 of simulation model 300″, for example, by embedding within the HDL file of top-level entity 302 a configuration specification statement specifying LDial 524 or a configuration file reference statement referencing a separate configuration file containing a configuration specification statement specifying LDial 524. In either case, an exemplary configuration specification statement for LDial 524 is as follows:

LDial bus ratio (FXU0.A0.SIG1, FXU0.A1.SIG1,        FXU0.B.C.SIG2(0..5),        FXU1.A0.SIG1, FXU1.A1.SIG1,        FXU1.B.C.SIG2(0..5),        FPU0.SIG3, SIG4(0..3)        ) =        {2:1 =>0b0, 0b0, 0x00,           0b0, 0b0, 0x00,           0b0, 0x0;        3:1 => 0b1, 0b1, 0x01,           0b1, 0b1, 0x01,           0b0, 0x1;        4:1 => 0b1, 0b1, 0x3F,           0b1, 0b1, 0x3F,           0b1, 0xF        };

The exemplary configuration specification statement given above begins with the keyword “LDial,” which specifies that the type of Dial being declared is an LDial, and the Dial name, which in this case is “bus ratio.” Next, the configuration specification statement enumerates the signal names whose states are controlled by the LDial. As indicated above, the signal identifier for each signal is specified hierarchically (e.g., FXU0.A0.SIG1 for signal 514 a 0) relative to the default scope of the associated design entity so that different signal instances having the same signal name are distinguishable. Following the enumeration of the signal identifiers, the configuration specification statement includes a mapping table listing the permitted enumerated input values of the LDial and the corresponding signal values for each enumerated input value. The signal values are associated with the signal names implicitly by the order in which the signal names are declared. It should again be noted that the signal states specified for all enumerated values are unique, and collectively represent the only legal patterns for the signal states.

Several different syntaxes can be employed to specify the signal states. In the example given above, signal states are specified in either binary format, which specifies a binary constant preceded by the prefix “0b”, or in hexadecimal format, which specifies a hexadecimal constant preceded by the prefix “0x”. Although not shown, signal states can also be specified in integer format, in which case no prefix is employed. For ease of data entry, the configuration specification language of ECAD system 35 also preferably supports a concatenated syntax in which one constant value, which is automatically extended with leading zeros, is utilized to represent the concatenation of all of the desired signal values. In this concatenated syntax, the mapping table of the configuration specification statement given above can be rewritten as:

{2:1 =>    0,  3:1 =>    0x183821,  4:1 =>    0x1FFFFF }; in order to associate enumerated input value 2:1 with a concatenated bit pattern of all zeros, to associate the enumerated input value 3:1 with the concatenated bit pattern ‘0b110000011100000100001’, and to associate the enumerated input value 4:1 with a concatenated bit pattern of all ones.

Referring now to FIG. 4A, there is depicted a diagrammatic representation of an Integer Dial (“IDial”) in accordance with a preferred embodiment of the present invention. Like an LDial, an IDial directly specifies the value loaded into each of one or more configuration latches 605 by indicating within mapping table 603 a correspondence between each input value received at an input 602 and an output value for each output 604. However, unlike LDials, which can only receive as legal input values the enumerated input values explicitly set forth in their mapping tables 503, the legal input value set of an IDial includes all possible integer values within the bit size of output 604. (Input integer values containing fewer bits than the bit size of output(s) 604 are right justified and extended with zeros to fill all available bits.) Because it would be inconvenient and tedious to enumerate all of the possible integer input values in mapping table 603, mapping table 603 preferably simply indicates the manner in which the integer input value received at input 602 is applied to the one or more outputs 604.

IDials are ideally suited for applications in which one or more multi-bit registers must be initialized and the number of legal values includes most values of the register(s). For example, if a 4-bit configuration register comprising 4 configuration latches and an 11-bit configuration register comprising 11 configuration latches were both to be configured utilizing an LDial, the designer would have to explicitly enumerate up to 215 input values and the corresponding output bit patterns in the mapping table of the LDial. This case can be handled much more simply with an IDial utilizing the following configuration specification statement:

-   -   IDial cnt_value (sig1(0 . . . 3), sig2(0 . . . 10));         In the above configuration specification statement, “IDial”         declares the configuration entity as an IDial, “cnt_value” is         the name of the IDial, “sig1” is a 4-bit signal output by the         4-bit configuration register and “sig2” is an 11-bit signal         coupled to the 11-bit configuration register. In addition, the         ordering and number of bits associated with each of sig1 and         sig2 indicate that the 4 high-order bits of the integer input         value will be utilized to configure the 4-bit configuration         register associated with sig1 and the 11 lower-order bits will         be utilized to configure the 11-bit configuration register         associated with sig2. Importantly, although mapping table 603         indicates which bits of the integer input values are routed to         which outputs, no explicit correspondence between input values         and output values is specified in mapping table 603.

IDials may also be utilized to specify the same value for multiple replicated configuration registers, as depicted in FIG. 4B. In the illustrated embodiment, an IDial 610, which can be described as an IDial “splitter”, specifies the configuration of three sets of replicated configuration registers each comprising 15 configuration latches 605 based upon a single 15-bit integer input value. An exemplary configuration specification statement for instantiating IDial 610 may be given as follows:

IDial cnt_value(A0.sig1(0..7), A0.sig2(8..14);          A1.sig1(0..7), A1.sig2(8..14);          A3.sig1(0..7), A3.sig2(8..14)         ); In the above configuration specification statement, “IDial” declares the configuration entity as an IDial, and “cnt_value” is the name of the IDial. Following the IDial name are three scope fields separated by semicolons (“;”). Each scope field indicates how the bits of the input integer value are applied to particular signals. For example, the first scope field specifies that the 8 high-order bits of the integer input value will be utilized to configure the 8-bit configuration register associated with the signal A0.sig1 and the 7 lower-order bits will be utilized to configure the 7-bit configuration register associated with A0.sig2. The second and third scope fields specify that the corresponding configuration registers within design entities A1 and A3 will be similarly configured. Importantly, the integer input bits can be allocated differently in each scope field as long as the total number of bits specified in each scope field is the same.

Although the configuration of a digital design can be fully specified utilizing LDials alone or utilizing LDials and IDials, in many cases it would be inefficient and inconvenient to do so. In particular, for hierarchical digital designs such as that illustrated in FIG. 3C, the use of LDials and/or IDials alone would force many Dials to higher levels of the design hierarchy, which, from an organizational standpoint, may be the responsibility of a different designer or design group than is responsible for the design entities containing the configuration latches controlled by the Dials. As a result, proper configuration of the configuration latches would require not only significant organizational coordination between design groups, but also that designers responsible for higher levels of the digital design learn and include within their HDL files details regarding the configuration of lower level design entities. Moreover, implementing Dials at higher levels of the hierarchy means that lower levels of the hierarchy cannot be independently simulated since the Dials controlling the configuration of the lower level design entities are not contained within the lower level design entities themselves.

In view of the foregoing, the present invention recognizes the utility of providing a configuration entity that supports the hierarchical combination of Dials to permit configuration of lower levels of the design hierarchy by lower-level Dials and control of the lower-level Dials by one or more higher-level Dials. The configuration specification language of the present invention terms a higher-level Dial that controls one or more lower-level Dials as a Control Dial (“CDial”).

Referring now to FIG. 5A, there is depicted a diagrammatic representation of a CDial 700 a in accordance with the present invention. CDial 700 a, like all Dials, preferably has a single input 702, one or more outputs 704, and a mapping table 703 that maps each input value to a respective associated output value for each output 704. Unlike LDials and IDials, which directly specify configuration latches, a CDial 700 does not directly specify configuration latches. Instead, a CDial 700 controls one or more other Dials (i.e., CDials and/or LDials and/or IDials) logically coupled to CDial 700 in an n-way “Dial tree” in which each lower-level Dial forms at least a portion of a “branch” that ultimately terminates in “leaves” of configuration latches. Dial trees are preferably constructed so that no Dial is instantiated twice in any Dial tree.

In the exemplary embodiment given in FIG. 5A, CDial 700 a receives at input 702 an enumerated input value (i.e., a string) among a set of legal values including “A”, . . . , “N”. If CDial 700 a (or an LDial or IDial) is a top-level Dial (i.e., there are no Dials “above” it in a Dial tree), CDial 700 a receives the enumerated input value directly from software (e.g., simulation software or firmware). Alternatively, if CDial 700 a forms part of a “branch” of a dial tree, then CDial 700 a receives the enumerated input value from the output of another CDial. For each legal enumerated input value that can be received at input 702, CDial 700 a specifies a selected enumerated value or bit value for each connected Dial (e.g., Dials 700 b, 500 and 600) in mapping table 703. The values in mapping table 703 associated with each output 704 are interpreted by ECAD system 35 in accordance with the type of lower-level Dial coupled to the output 704. That is, values specified for LDials and CDials are interpreted as enumerated values, while values specified for IDials are interpreted as integer values. With these values, each of Dials 700 b, 500 and 600 ultimately specifies, either directly or indirectly, the values for one or more configuration latches 705.

With reference now to FIG. 5B, there is illustrated another diagrammatic representation of a simulation model containing a Dial tree including a top-level CDial that controls multiple lower-level LDials. As indicated by prime notation, simulation model 300′″ of FIG. 5B includes the same design entities arranged in the same hierarchical relation as simulation model 300 of FIG. 2 and contains the same configuration latches and associated signals as simulation model 300″ of FIG. 3C.

As shown, simulation model 300′″ of FIG. 5B includes a top-level CDial 710 associated with top-level design entity 302. Simulation model 300′″ further includes four LDials 712 a, 712 b, 714 and 716. LDial 712 a, which is associated with entity instantiation A0 304 a, controls the signal states of each signal sig1 514 a, which is determined by a respective configuration latch 512 a, and the signal state of signal sig2 522 a, which is determined by configuration latch 520 a. LDial 712 b, which is a replication of LDial 712 a associated with entity instantiation A1 304 b, similarly controls the signal states of each signal sig1 514 b, which is determined by a respective configuration latch 512 b, and the signal state of signal sig2 522 b, which is determined by configuration latch 520 b. LDial 714, which is associated with top-level entity 302, controls the signal state of signal sig4 532, which is determined by configuration latch 530. Finally, LDial 716, which is associated with entity instantiation FPU0 314, controls the signal state of signal sig3 536, which is determined by configuration latch 534. Each of these four LDials is controlled by CDial 710 associated with top-level entity 302.

As discussed above, CDial 710 and each of the four LDials depicted in FIG. 5B can be instantiated within the associated design entity, for example, by embedding a configuration specification statement (or a configuration file reference statement pointing to a configuration file containing a configuration specification statement) within the HDL file of the associated design entity. An exemplary configuration specification statement utilized to instantiate each Dial shown in FIG. 5B is given below:

CDial BusRatio (FXU0.BUSRATIO, FXU1.BUSRATIO,           FPU0.BUSRATIO, BUSRATIO)=        {2:1 => 2:1, 2:1, 2:1, 2:1;         3:1 => 3:1, 3:1, 3:1, 3:1;        4:1 => 4:1, 4:1, 4:1, 4:1        }; LDial BusRatio (A0.sig1, A1.sig1, B.C.sig2(0..5)) =        {2:1 => 0b0, 0b0, 0x00;         3:1 => 0b1, 0b1, 0x01;        4:1 => 0b1, 0b1, 0x3F;        }; LDial BusRatio (sig3) =        {2:1 => 0b0;        3:1 => 0b0;        4:1 => 0b1        }; LDial BusRatio (sig4(0..3)) =        {2:1 => 0x0;         3:1 => 0x1;         4:1 => 0xF        };

By implementing a hierarchical Dial tree in this manner, several advantages are realized. First, the amount of software code that must be entered is reduced since the automatic replication of LDials 712 within FXU entity instantiations 304 a and 304 b allows the code specifying LDials 712 to be entered only once. Second, the organizational boundaries of the design process are respected by allowing each designer (or design team) to specify the configuration of signals within the design entity for which he is responsible. Third, coding of upper level Dials (i.e., CDial 710) is greatly simplified, reducing the likelihood of errors. Thus, for example, the CDial and LDial collection specified immediately above performs the same function as the “large” LDial specified above with reference to FIG. 3C, but with much less complexity in any one Dial.

Many Dials, for example, LDials utilized to disable a particular design entity in the event an uncorrectable error is detected, have a particular input value that the Dial should have in nearly all circumstances. For such Dials, the configuration specification language of the present invention permits a designer to explicitly specify in a configuration specification statement a default input value for the Dial. In an exemplary embodiment, a Default value is specified by including “=default value” following the specification of a Dial and prior to the concluding semicolon. For example, a default value for a CDial, can be given as follows:

CDial BusRatio (FXU0.BUSRATIO, FXU1.BUSRATIO,           FPU0.BUSRATIO, BUSRATIO)=        {2:1 => 2:1, 2:1, 2:1, 2:1;        3:1 => 3:1, 3:1, 3:1, 3:1;        4:1 => 4:1, 4:1, 4:1, 4:1        } = 2:1; It should be noted that for CDials and LDials, the specified default value is required to be one of the legal enumerated values, which are generally (i.e., except for Switches) listed in the mapping table. For Switches, the default value must be one of the predefined enumerated values of “ON” and “OFF”.

A default value for an IDial can similarly be specified as follows:

IDial cnt_value(A0.sig1(0..7), A0.sig2(8..14);         A1.sig1(0..7), A1.sig2(8..14);         A3.sig1(0..7), A3.sig2(8..14)         ) = 0x7FFF; In this case, a constant, which can be given in hexadecimal, decimal or binary format, provides the default output value of each signal controlled by the IDial. In order to apply the specified constant to the indicated signal(s), high order bits are truncated or padded with zeros, as needed.

The configuration specification language of the present invention also permits control of the time at which particular default values are applied. Control of the application of defaults is important, for example, in simulating or executing in hardware the boot sequence for an integrated circuit. During the initial stages of the boot sequence, the clock signals to different sections of the integrated circuit may be started at different times, meaning that latches in different sections of the integrated circuit must be loaded at different times in accordance with the specified Dial default values.

In accordance with the present invention, control of the timing of the application of default values is supported through the association of one or more phase identifiers (IDs) with a default value. Phase IDs are strings that label collections of Dials to which default values should be applied substantially concurrently. Multiple phase IDs may be associated with a particular Dial to promote flexibility. For example, in different system configurations, the boot sequence for a constituent integrated circuit may be different. Accordingly, it may be necessary or desirable to apply a default value to a particular Dial during different phases, depending upon the system configuration.

In one exemplary syntax, one or more phase IDs (e.g., phaseid0 and phaseid1) can optionally be specified in a comma delimited list enclosed by parenthesis and following a default declaration in a Dial declaration statement as follows:

CDial BusRatio (FXU0.BUSRATIO, FXU1.BUSRATIO,           FPU0.BUSRATIO, BUSRATIO)=        {2:1 => 2:1, 2:1, 2:1, 2:1;        3:1 => 3:1, 3:1, 3:1, 3:1;        4:1 => 4:1, 4:1, 4:1, 4:1        } = 2:1 (phaseid0, phaseid1); It is preferably an error to specify a phase ID for a Dial for which no default value is specified, and as noted above, the specification of any phase ID is preferably entirely optional, as indicated by the exemplary CDial and IDial declarations given previously.

The use of default values for Dials is subject to a number of rules. First, a default value may be specified for any type of Dial including LDials, IDials (including those with split outputs) and CDials. Default values are preferably not supported for Dial groups (which are discussed below with respect to FIGS. 6A-6B). Second, if default values are specified for multiple Dials in a multiple-level Dial tree, only the highest-level default value affecting each “branch” of the Dial tree is applied (including that specified for the top-level Dial), and the remaining default values, if any, are ignored. Despite this rule, it is nevertheless beneficial to specify default values for lower-level Dials in a Dial tree because the default values may be applied in the event a smaller portion of a model is independently simulated, as discussed above. In the event that the combination of default values specified for lower-level Dials forming the “branches” of a Dial tree do not correspond to a legal output value set for a higher-level Dial, the compiler will flag an error. Third, a default value is overridden when a Dial receives an input to actively set the Dial.

By specifying default values for Dials, a designer greatly simplifies use of Dials by downstream organizational groups by reducing the number of Dials that must be explicitly set for simulation or hardware configuration. In addition, as discussed further below, use of default values assists in auditing which Dials have been actively set.

As described above, every Dial has a one-to-one mapping between each of its input values and a unique output value of the Dial. In other words, each input value has a unique output value different than the output value for any other input value. For CDials and LDials, the mapping table must explicitly enumerate each legal input value and its associated mapping. The requirement that the input values must be explicitly enumerated in the mapping table limits the overall complexity of any given LDial or CDial. For example, consider the case of an integrated circuit (e.g., a memory controller) containing 10 to 20 configuration registers each having between 5 and 20 legal values. In many cases, these registers have mutual dependencies—the value loaded in one register can affect the legal possibilities of one or more of the other registers. Ideally, it would be convenient to specify values for all of the registers utilizing a Dial tree controlled by a single CDial. In this manner, the configuration of all of the 10 to 20 registers could be controlled as a group.

Unfortunately, given the assumptions set forth above, the 10 to 20 registers collectively may have over 300,000 legal combinations of values. The specification of a CDial in such a case, although theoretically possible, is undesirable and practically infeasible. Moreover, even if a looping construct could be employed to automate construction of the configuration specification statement of the CDial, the configuration specification statement, although informing simulation software which input values are legal, would not inform users how to set a CDial of this size.

In recognition of the foregoing, the configuration specification language of the present invention provides a “Dial group” construct. A Dial group is a collection of Dials among which the designer desires to create an association. The runtime APIs utilized to provide Dial input values observe this association by preventing the individual Dials within a Dial group from being set individually. In other words, all Dials in a Dial group must be set at the same time so that individual Dials are not set independently without concern for the interactions between Dials. Because software enforces an observance of the grouping of the Dials forming a Dial group, use of Dial groups also provides a mechanism by which a designer can warn the “downstream” user community that an unstated set of interdependencies exists between the Dials comprising the Dial group.

With reference now to FIG. 6A, there is illustrated a diagrammatic representation of a Dial group 1100 a. A Dial group 1100 a is defined by a group name 1102 (e.g., “GroupG”) and a Dial list 1104 listing one or more Dials or other Dial groups. Dial groups do not have any inputs or outputs. The Dials listed within Dial list 1104, which are all top-level Dials 1110 a-1110 f, may be LDials, CDials and/or IDials.

FIG. 6A illustrates that a Dial group 1100 a may be implemented as a hierarchical Dial group that refers to one or more other Dial groups 1100 b-1100 n in its Dial list 1104. These lower-level Dial groups in turn refer to one or more top-level Dials 1110 g-1110 k and 1110 m-1110 r (or other Dial groups) in their respective Dial lists.

One motivation for implementing Dial groups hierarchically is to coordinate configuration of groups of Dials spanning organizational boundaries. For example, consider a digital system in which 30 Dials logically belong in a Dial group and 10 of the Dials are contained within a first design entity that is the responsibility of a first designer and 20 of the Dials are contained within a second design entity that is the responsibility of a second designer. Without a hierarchical Dial group, a single Dial group explicitly listing all 30 Dials in its Dial list 1104 would have to be specified at a higher level of the design hierarchy encompassing both of the first and second design entities. This implementation would be inconvenient in that the designer (or design team) responsible for the higher-level design entity would have to know all of the related Dials in the lower-level design entities and specifically identify each of the 30 Dials in the Dial list 1104 of the Dial group.

An alternative hierarchical approach would entail creating a first Dial group containing the 10 Dials within the first design entity, a second Dial group containing the Dials within the second design entity, and a third higher-level Dial group that refers to the first and second Dial groups. Importantly, the Dial list 1104 of the higher-level Dial group must only refer to the two lower-level Dial groups, thus shielding designers responsible for higher levels of the design hierarchy from low-level details. In addition, code maintenance is reduced since changing which Dials belong to the two lower-level Dial groups would not affect the Dial list 1104 of the upper-level Dial group.

Dial groups are subject to a number of rules. First, no Dial or Dial group may be listed in the Dial list 1104 of more than one Dial group. Second, a Dial group must refer to at least one Dial or other Dial group in its Dial list 1104. Third, in its Dial list 1104, a Dial group can only refer to Dials or Dial groups within its scope, which by convention (and like the concept of scope as applied to Dials) is that of its associated design entity (i.e., the design entity itself and any lower level design entity within the design entity). Fourth, each Dial referred to in a Dial list 1104 of a Dial group must be a top-level Dial.

Referring now to FIG. 6B, there is depicted an exemplary simulation model 1120 illustrating the use of Dial groups. Exemplary simulation model 1120 includes a top-level design entity 1122 having instantiation identifier “TOP:TOP”. Within top-level design entity 1122, two design entities 1124 and 1126 are instantiated, which have entity names FBC and L2, respectively. FBC entity instantiation 1124 in turn instantiates a Dial instance 1130 having Dial name “C”, a Z entity instantiation 1132 containing a Dial instance 1134 having Dial name “B”, and two instantiations of entity X 1136, which are respectively named “X0” and “X1”. Each entity X instantiation 1136 contains two entity Y instantiations 1138, each further instantiating a Dial instance 1140 having Dial name “A”. L2 entity instantiation 1126 contains a Dial instance 1150 having Dial name “D” and two entity L instantiations 1152, each containing a Dial instance 1154 having Dial name “E”.

As shown, FBC entity instantiation 1124 has an associated Dial group instance 1160 having a group name “F”. As indicated by arrows, Dial group instance 1160 includes each of Dials instances 1130, 1134 and 1140 within FBC entity instantiation 1124. L2 entity instantiation 1126 similarly has an associated Dial group instance 1162 that includes each of Dial instances 1150 and 1154 within L2 entity instantiation 1126. Both of these Dial group instances in turn belong to a higher-level Dial group instance 1164 having group name “H”, which is associated with top-level design entity 1122.

Each Dial group instance is created, for example, by including within the HDL file of the associated design entity an appropriate configuration statement. For example, exemplary syntax for configuration statements creating Dial groups “F”, “G” and “H” are respectively given as follows:

GDial F(C, [Z].B, [Y].A); GDial G(D, [L].E); GDial H(FBC.F, L2.G);

In each configuration statement, a Dial group is declared by the keyword “GDial”, which is followed by string (e.g., “F”) representing the group name. Within the parenthesis following the group name, the Dial list for the Dial group is specified. As indicated in the configuration statement for Dial group “H”, the Dial list for a hierarchical Dial group specifies other Dial groups in the same manner as Dials. It should also be noted that the compact dial expression syntax discussed herein can be employed in specifying Dials or Dial groups in the Dial list, as indicated in the configuration statements for Dial groups “F” and “G”.

With reference again to FIG. 3C, recall that an exemplary configuration specification statement for LDial 524 includes a parenthetical signal enumeration of the form:

LDial bus ratio (FXU0.A0.SIG1, FXU0.A1.SIG1,        FXU0.B.C.SIG2(0..5),        FXU1.A0.SIG1, FXU1.A1.SIG1,        FXU1.B.C.SIG2(0..5),        FPU0.SIG3, SIG4(0..3)        ) =        ... It should be noted that the signal enumeration section of the configuration specification statement individually, hierarchically and explicitly enumerates the signal identifier of each signal instance configured by the Dial, beginning from the scope of the design entity with which the Dial is associated (which by convention is the design entity in whose HDL file the configuration specification statement or configuration reference statement instantiating the Dial is embedded). This syntax is referred to herein as a “full expression” of a signal identifier. Employing “full expression” syntax in the signal enumeration section of the configuration specification statement for an LDial or IDial or in the Dial enumeration section of the configuration specification statement of a CDial requires the designer to know and correctly enter the hierarchical identifier for each instance of a signal (or lower-level Dial) controlled by the Dial. Consequently, if a new instance of the same signal (or lower-level Dial) were later added to the digital design, the designer must carefully review the configuration specification statement of the Dial(s) referencing other instances of the same signal (or Dial) and update the signal (or Dial) enumeration section to include the full expression of the newly added instance.

In order to reduce the amount of input required to input the signal (or Dial) enumeration sections of configuration specification statements and to reduce the burden of code maintenance as new signal and Dial instances are added to the digital design, an ECAD system 35 in accordance with at least some embodiments of the present invention also supports a “compact expression” syntax for the signal (or Dial) enumeration sections of configuration specification statements, as described in of U.S. patent application Ser. No. 10/902,628. This syntax is referred to herein more specifically as “compact signal expression” when applied to the configuration specification statements of LDials and IDials and is referred to as “compact Dial expression” when referring to the configuration specification statements of CDials or Dial groups.

In the foregoing description, functional signal(s) that are referenced by a configuration specification statement generally reside within the design entity with which the Dial is associated or within the associated design entity's descendent entity or entities. The practice of referring to signals within the associated design entity and/or its descendants (which is referred to herein as the “scope” of the associated design entity) can further be enforced, if desired, during the model build process shown in FIG. 7. One rationale for enforcing a “scope” rule during the model build process is that if all signal references of configuration specification statements are confined to the scope of the associated design entity, the signal(s) referenced will generally (with some exceptions) be present in the simulation model. If, however, references outside of the scope of the associated design entity are permitted, at least some references may refer to signals or configuration entities that are not present within the given simulation model.

For example, referring again to FIG. 3C, assume a designer of design entity FPU wants to create a Dial that references a signal within design entity FXU. If signal references are limited to the scope of the design entity associated with a Dial, then the configuration specification statement defining the Dial must be contained within or otherwise referenced by or attached to the HDL file for TOP design entity 302 (i.e., a level of the design hierarchy that encloses all the necessary signals). However, this requirement may be inconvenient because in many cases the “owner” controlling the content and functionality of a lower level design entity (e.g., design entity FPU) during the design process may not be the owner of the higher level design entities (e.g., TOP). Further, the requirement may necessitate the separation of configuration specification statements describing logically related Dials into different HDL files, increasing the difficulty of managing the configuration code. Thus, in at least some embodiments, it is desirable to permit the configuration specification statements of a Dial or Dial group to reference signals or Dials outside of the scope of the Dial or Dial group.

One exemplary syntax that permits out-of-scope references to signals can be given with reference to the scope of design entity FPU as follows:

sig3 // Refers to sig3 536 (since it is at the hierarchy level of design // entity FPU) !.sig4(0..3) // Refers to signal sig4(0..3) 532 in design entity TOP 302, // where “!” indicates moving up one level of the design // hierarchy from the scope of the design entity !.FXU0.A0.sig1 // Refers to sig1 514a0 Similarly, signal sig1 514 a 0 can be referenced from the scope of design entity FXU0.B.C as follows: !.!.A0.sig1.

As noted above, if out-of-scope references are permitted during the model build process, there are some situations in which references to signal and configuration entity names cannot be resolved within the simulation model. For example, in a simulation model including only design entity C 312, any of the out-of-scope references will fail to find the referenced signals or configuration entities because, for that simulation model, the higher hierarchy levels simply do not exist. In a preferred embodiment, identifying a referenced signal or configuration entity that cannot be resolved due to an out-of-scope reference is not flagged as an error, but entails special handling as described further herein.

It should also be noted that, in certain cases, even in-scope signal and configuration entity references may fail to resolve. For example, VHDL supports definition of multiple alternative architectures for an entity and the use of a VHDL configuration to specify which of the multiple architectures is to be used for the entity. A VHDL configuration can also be used to replace one entity with another entity or OPEN an entity to leave it empty.

If a design entity is OPEN any reference to a signal supposed to be within the design entity will obviously fail to resolve. As above, this situation is not considered an error, and any configuration entity or entities that depends on an unresolved signal reference must be appropriately handled. If, however, a signal reference resolves for one or more architectures of a design entity and fails to resolve for at least one other architecture of the design entity, it may be desirable to flag this situation as an error in at least some cases, depending, for example, upon the designer's preference.

Again assuming the scope of design entity FXU0.B.C of FIG. 3C, an exemplary syntax for expressing that it is permissible for a reference to sig1 514 a 0 to fail to resolve without error is given as follows:

-   -   !.!.FXU0.A0.sig1#         In this exemplary syntax, the # character is placed adjacent to         (i.e., without an intervening white space) a signal or         configuration entity reference to identify that signal as able         to fail to resolve without error. In this exemplary syntax, any         reference that is not so designated will generate an error         during the model build process described below with reference to         FIG. 7 if it fails to resolve. In at least some embodiments,         this syntax can be extended to permit the designer to explicitly         define a set of one or more architectures for which a failure to         resolve will cause an error and/or a set of one or more         architectures for which a failure to resolve will not cause an         error.

Referring now to FIG. 7, there is depicted a high level flow diagram of a model build process in which HDL files containing configuration statements are compiled to obtain a simulation executable model and a simulation configuration database for a digital design. The process begins with one or more design entity HDL source code files 800, which include configuration specification statements and/or configuration file reference statements, and, optionally, one or more configuration specification reference files 802. HDL compiler 804 processes HDL file(s) 800 and configuration specification file(s) 802, if any, beginning with the top level entity of a simulation model and proceeding in a recursive fashion through all HDL file(s) 800 describing a complete simulation model. As HDL compiler 804 processes each HDL file 800, HDL compiler 804 creates “markers” in the design intermediate files 806 produced in memory to identify configuration statements embedded in the HDL code and any configuration specification files referenced by an embedded configuration file reference statement.

Thereafter, the design intermediate files 806 in memory are processed by a configuration compiler 808 and model build tool 810 to complete the model build process. Model build tool 810 processes design intermediate files 806 into a simulation executable model 816, that when executed, models the logical functions of the digital design, which may represent, for example, a portion of an integrated circuit, an entire integrated circuit or module, or a digital system including multiple integrated circuits or modules. In this processing, model build tool 810 preferably generates an m-way tree indicating the hierarchical relationships between the design entities comprising the simulation model.

Configuration compiler 808 processes the configuration specification statements marked in design intermediate files 806 and creates from those statements a configuration documentation file 812 and a configuration database 814. Configuration documentation file 812 lists, in human-readable format, information describing the Dials associated with the simulation model. The information includes the Dials' names, their mapping tables, the structure of Dial trees, if any, instance information, etc. In addition, as noted above, configuration documentation file 812 includes strings contained in comment statements describing the functions and settings of the Dials in the digital design. In this manner, configuration documentation suitable for use with both a simulation model and a hardware implementation of a digital design is aggregated in a “bottom-up” fashion from the designers responsible for creating the Dials. The configuration documentation is then made available to all downstream organizational groups involved in the design, simulation, laboratory hardware evaluation, and commercial hardware implementation of the digital design.

Configuration database 814 preferably contains the m-way tree generated by model build tool 810 that describes the hierarchical relationships of the design entities within simulation executable model 816, as well as a number of data structures pertaining to Dials and other configuration entities. As described in detail below, these data structures include, without limitation, Dial data structures describing Dial entities, latch data structures, and Dial instance data structures. These data structures associate particular Dial inputs with particular configuration values used to configure the digital design (i.e., simulation executable model 816). In a preferred embodiment, the configuration values can be specified in terms of either signal states or configuration latch values, and the selection of which values are used is user-selectable. Configuration database 814 is accessed via Application Programming Interface (API) routines during simulation of the digital design utilizing simulation executable model 816 and is further utilized to generate similar configuration databases for configuring physical realizations of the digital design. In a preferred embodiment, the APIs are designed so that only top-level Dials (i.e., LDials, IDials or CDials without a CDial logically “above” them) can be set and all Dial values can be read.

Now that basic types of Dials, syntax for their specification, and the application of Dial groups have been described, a description of an exemplary implementation of configuration database 814 and its use will be provided. To promote understanding of the manner in which particular Dial instantiations (or multiple instantiations of a Dial) can be accessed in configuration database 814, a nomenclature for Dials within configuration database 814 will be described.

The nomenclature employed in a preferred embodiment of the present invention first requires a designer to uniquely name each Dial specified within any given design entity, i.e., the designer cannot declare any two Dials within the same design entity with the same Dial name. Observing this requirement prevents name collisions between Dials instantiated in the same design entity and promotes the arbitrary re-use of design entities in models of arbitrary size. This constraint is not too onerous in that a given design entity is usually created by a specific designer at a specific point in time, and maintaining unique Dial names within such a limited circumstance presents only a moderate burden.

Because it is desirable to be able to individually access particular instantiations of a Dial entity that may have multiple instantiations in a given simulation model (e.g., due to replication), use of a Dial name alone is not guaranteed to uniquely identify a particular Dial entity instantiation in a simulation model. Accordingly, in a preferred embodiment, the nomenclature for Dials leverages the unique instantiation identifier of the associated design entity required by the native HDL to disambiguate multiple instances of the same Dial entity with an “extended Dial identifier” for each Dial within the simulation model.

As an aside, it is recognized that some HDLs do not strictly enforce a requirement for unique entity names. For example, conventional VHDL entity naming constructs permit two design entities to share the same entity name, entity_name. However, VHDL requires that such identically named entities must be encapsulated within different VHDL libraries from which a valid VHDL model may be constructed. In such a circumstance, the entity_name is equivalent to the VHDL library name concatenated by a period (“.”) to the entity name as declared in the entity declaration. Thus, pre-pending a distinct VHDL library name to the entity name disambiguates entities sharing the same entity name. Most HDLs include a mechanism such as this for uniquely naming each design entity.

In a preferred embodiment, an extended Dial identifier that uniquely identifies a particular instantiation of a Dial entity includes three fields: an instantiation identifier field, a design entity name, and a Dial name. The extended Dial identifier may be expressed as a string in which adjacent fields are separated by a period (“.”) as follows:

<instantiation identifier>.<design entity name>.<Dial name>

In the extended Dial identifier, the design entity field contains the entity name of the design entity in which the Dial is instantiated, and the Dial name field contains the name declared for the Dial in the Dial configuration specification statement. As described above, the instantiation identifier specified in the instantiation identifier field is a sequence of instantiation identifiers, proceeding from the top-level entity of the simulation model to the direct ancestor design entity of the given Dial instance, with adjacent instance identifiers separated by periods (“.”). Because no design entity can include two Dials of the same name, the instantiation identifier is unique for each and every instance of a Dial within the model.

The uniqueness of the names in the design entity name field is a primary distinguishing factor between Dials. By including the design entity name in the extended Dial identifier, each design entity is, in effect, given a unique namespace for the Dials associated with that design entity, i.e., Dials within a given design entity cannot have name collisions with Dials associated with other design entities. It should also be noted that it is possible to uniquely name each Dial by using the instantiation identifier field alone. That is, due to the uniqueness of instantiation identifiers, Dial identifiers formed by only the instantiation identifier field and the Dial name field will be necessarily unique. However, such a naming scheme does not associate Dials with a given design entity. In practice, it is desirable to associate Dials with the design entity in which they occur through the inclusion of the design entity field because all the Dials instantiations can then be centrally referenced without the need to ascertain the names of all the design entity instantiations containing the Dial.

As noted above, use of extended Dial identifiers permits the unique identification of a particular instantiation of a Dial and permits the re-use of design entities within any arbitrary model without risk of Dial name collisions. For example, referring again to FIG. 6B, Dial A entity instantiations 1140 a 0, 1140 a 1, 1140 b 0 and 1140 b 1 can be respectively uniquely identified by the following extended Dial identifiers:

FBC.X0.Y0.Y.A FBC.X0.Y1.Y.A FBC.X1.Y0.Y.A FBC.X1.Y1.Y.A

As described above, the configuration specification language of the present invention advantageously permits the specification of the output values of LDials and IDials by reference to signal names (e.g., “sig1”). As noted above, a key motivation for this feature is that designers tend to think in terms of configuring operative signals to particular signal states, rather than configuring the associated configuration latches. In practice, however, a signal that a designer desires to configure to a particular state may not be directly connected to the output of an associated configuration latch. Instead, a signal to be configured may be coupled to an associated configuration latch through one or more intermediate circuit elements, such as buffers and inverters. Rather than burdening the designer with manually tracing back each configurable signal to an associated configuration latch and then determining an appropriate value for the configuration latch, configuration compiler 808 automatically traces back a specified signal to the first storage element (i.e., configuration latch) coupled to the signal and performs any necessary inversions of the designer-specified signal state value to obtain the proper value to load into the configuration latch, as described in U.S. patent application Ser. No. 10/902,628.

With an understanding of a preferred nomenclature of Dials, reference is now made to FIG. 8, which is a diagrammatic representation of an exemplary format for a configuration database 814 created by configuration compiler 808. In this exemplary embodiment, configuration database 814 includes at least four different types of data structures: Dial definition data structures (DDDS) 1200, Dial instance data structures (DIDS) 1202, latch data structures 1204 and top-level pointer array 1206. Configuration database 814 may optionally include additional data structures, such as Dial pointer array 1208, latch pointer array 1210, instance pointer array 1226 and other data structures depicted in dashed-line illustration, which may alternatively be constructed in volatile memory when configuration database 814 is loaded, as described further below. Generating these additional data structures only after configuration database 814 is loaded into volatile memory advantageously promotes a more compact configuration database 814.

A respective Dial definition data structure (DDDS) 1200 is created within configuration database 814 for each Dial or Dial group in the digital system. Preferably, only one DDDS 1200 is created in configuration database 814 regardless of the number of instantiations of the Dial (or Dial group) in the digital system. As discussed below, information regarding particular instantiations of a Dial described in a DDDS 1200 is specified in separate DIDSs 1202.

As shown, each DDDS 1200 includes a type field 1220 denoting whether DDDS 1200 describes a Dial or Dial group, and if a Dial, the type of Dial. In one embodiment, the value set for type field 1220 includes “G” for Dial group, “I” for integer Dial (IDial), “L” for latch Dial (LDial), and “C” for control Dial (CDial). DDDS 1200 further includes a name field 1222, which specifies the name of the Dial or Dial group described by DDDS 1200. This field preferably contains the design entity name of the Dial (or Dial group), followed by a period (“.”), followed by the name of Dial (or Dial group) given in the configuration specification statement of the Dial (or Dial group). The contents of name field 1222 correspond to the design entity name and Dial name fields of the extended dial identifier for the Dial.

DDDS 1200 also includes a mapping table 1224 that contains the mapping from the input of the given Dial to its output(s), if required. For LDials and CDials, mapping table 1224 specifies relationships between input values and output values much like the configuration specification statements for these Dials. For Dial groups and IDials not having a split output, mapping table 1220 is an empty data structure and is not used. In the case of an IDial with a split output, mapping table 1220 specifies the width of the replicated integer field and the number of copies of that field. This information is utilized to map the integer input value to the various copies of the integer output fields.

Finally, DDDS 1200 may include an instance pointer array 1226 containing one or more instance pointers 1228 a-1228 n pointing to each instance of the Dial or Dial group defined by the DDDS 1200. Instance pointer array 1226 facilitates access to multiple instances of a particular Dial or Dial group.

As further illustrated in FIG. 8, configuration database 814 contains a DIDS 1202 corresponding to each Dial instantiation or Dial group instantiation within a digital design. Each DIDS 1202 contains a definition field 1230 containing a definition pointer 1231 pointing to the DDDS 1200 of the Dial for which the DIDS 1202 describes a particular instance. Definition pointer 1231 permits the Dial name, Dial type and mapping table of an instance to be easily accessed once a particular Dial instance is identified.

DIDS 1202 further includes a parent field 1232 that, in the case of an IDial, CDial or LDial, contains a parent pointer 1233 pointing to the DIDS 1202 of the higher-level Dial instance, if any, having an output logically connected to the input of the corresponding Dial instance. In the case of a Dial group, parent pointer 1233 points to the DIDS 1202 of the higher-level Dial group, if any, that hierarchically includes the present Dial group. If the Dial instance corresponding to a DIDS 1202 is a top-level Dial and does not belong to any Dial group, parent pointer 1233 in parent field 1232 is a NULL pointer. It should be noted that a Dial can be a top-level Dial, but still belong to a Dial group. In that case, parent pointer 1233 is not NULL, but rather points to the DIDS 1202 of the Dial group containing the top-level Dial.

Thus, parent fields 1232 of the DIDSs 1202 in configuration database 814 collectively describe the hierarchical arrangement of Dial entities and Dial groups that are instantiated in a digital design. As described below, the hierarchical information provided by parent fields 1232 advantageously enables a determination of the input value of any top-level Dial given the configuration values of the configuration latches ultimately controlled by that top-level Dial.

Instance name field 1234 of DIDS 1202 gives the fully qualified instance name of the Dial instance described by DIDS 1202 from the top-level design entity of the digital design. For Dial instances associated with the top-level entity, instance name field 1234 preferably contains a NULL string.

DIDS 1202 may further include a default field 1229, a phase ID field 1227, and a instance set field 1239. At compile time, configuration compiler 808 preferably initially inserts a default field 1229 into at least each DIDS 1202 for which the configuration specification statement for the associated Dial has a default specified. Default field 1229 stores the specified default value; if no default value is specified, default field 1229 is NULL or is omitted. Configuration compiler 808 subsequently analyzes configuration database 814 utilizing a recursive traversal and removes (or set to NULL) the default field 1229 of any Dial instance that has an ancestor Dial instance having a default. In this manner, default values of Dial instances higher in the hierarchy override defaults specified for lower level Dial instances. For each remaining (or non-NULL) default field 1229, configuration compiler 808 inserts into the DIDS 1202 a phase ID field 1227 for storing one or more phase IDs, if any, associated with the default value. The phase ID(s) stored within phase ID field 1227 may be specified within a Dial definition statement within an HDL file 800 or configuration specification file 802, or may alternatively be supplied by direct manipulation of configuration database 814 by a downstream user.

As indicated by dashed-line notation, an instance set field 1239 is preferably inserted within each DIDS 1302 in configuration database 814 when configuration database 814 is loaded into volatile memory. Instance set field 1239 is a Boolean-valued field that in initialized to FALSE and is updated to TRUE when the associated Dial instance is explicitly set.

Finally, DIDS 1202 includes an output pointer array 1236 containing pointers 1238 a-1238 n pointing to data structures describing the lower-level instantiations associated with the corresponding Dial instance or Dial group instance. Specifically, in the case of IDials and LDials, output pointers 1238 refer to latch data structures 1204 corresponding to the configuration latches coupled to the Dial instance. For non-split IDials, the configuration latch entity referred to by output pointer 1238 a receives the high order bit of the integer input value, and the configuration latch entity referred to by output pointer 1238 n receives the low order bit of the integer input value. In the case of a CDial, output pointers 1238 refer to other DIDSs 1202 corresponding to the Dial instances controlled by the CDial. For Dial groups, output pointers 1238 refer to the top-level Dial instances or Dial group instances hierarchically included within the Dial group instance corresponding to DIDS 1202. As discussed further below, one or more output pointers 1238 a-1238 n may be NULL pointers if the configuration statement instantiating the instance represented by DIDS 1202 references a signal or configuration entity that is not present in the simulation.

Configuration database 814 further includes a respective latch data structure 1204 for each configuration latch in simulation executable model 816 to which an output of an LDial or IDial is logically coupled. Each latch data structure 1204 includes a parent field 1240 containing a parent pointer 1242 to the DIDS 1200 of the LDial or IDial directly controlling the corresponding configuration latch. In addition, latch data structure 1204 includes a latch name field 1244 specifying the hierarchical latch name, relative to the entity containing the Dial instantiation identified by parent pointer 1242. For example, if an LDial X having an instantiation identifier a.b.c refers to a configuration latch having the hierarchical name “a.b.c.d.latch1”, latch name field 1244 will contain the string “d.latch1”. Prepending contents of an instance name field 1234 of the DIDS 1202 identified by parent pointer 1242 to the contents of a latch name field 1244 thus provides the fully qualified name of any instance of a given configuration latch configurable utilizing configuration database 814.

Still referring to FIG. 8, as noted above, configuration database 814 includes top-level pointer array 1206, and optionally, Dial pointer array 1208 and latch pointer array 1210. Top-level pointer array 1206 contains top-level pointers 1250 that, for each top-level Dial and each top-level Dial group, points to an associated DIDS 1202 for the top-level entity instance. Dial pointer array 1208 includes Dial pointers 1252 pointing to each DDDS 1200 in configuration database 814 to permit indirect access to particular Dial instances through Dial and/or entity names. Finally, latch pointer array 1210 includes latch pointers 1254 pointing to each latch data structure 1204 within configuration database 814 to permit easy access to all configuration latches.

With reference now to FIGS. 9A-9B, there is illustrated a high level logical flowchart of an exemplary process by which instances of configuration entities, such as Dials and Dial groups, are connected to instances of signals or configuration entities within a simulation model of a design in the presence of reference(s) to one or more possibly unavailable signals or configuration entities. The illustrated process may be performed, for example, by configuration compiler 808 during the model build process of FIG. 7 for each configuration statement that instantiates a configuration entity and includes a reference to an instance of a signal or a configuration entity. In the following description, the full expression syntax described above is assumed for simplicity.

The process of FIG. 9A begins at block 900 and then proceeds to block 902, which illustrates configuration compiler 808 determining, while parsing a configuration statement in design intermediate files 806 including a reference to a signal or a configuration entity, whether a next term in the statement includes a “#” character indicating that the reference to a signal or configuration entity name can fail to resolve without an error. If not, the process proceeds directly to block 906. If so, configuration compiler 808 sets a REF flag to signify that a failure to resolve the signal or Dial reference should not be treated as error, as shown at block 904, and then proceeds to block 906. At block 906, configuration compiler 808 determines whether it has reached the final signal name or Dial name in the reference. If so, the process proceeds through page connector D to block 940, which is described below. If, however, configuration compiler 808 determines that it has not reached the final signal or Dial name in the reference, the process passes to block 908.

Block 908 illustrates configuration compiler 808 determining whether the portion of the signal or configuration entity reference under consideration contains a “move up” character (e.g., a “!”) indicating a move upward in the design entity hierarchy. If not, the process proceeds to block 920, which is described below. If, however, the portion of the signal or configuration entity reference contains a “move up” character, configuration compiler 808 determines whether or not moving up one level in the design entity hierarchy would move beyond the top level of the design hierarchy defined by design intermediate files 806 (block 910). If so, the process passes through page connector E to block 946 of FIG. 9B, which is described below. If, however, configuration compiler 808 makes a negative determination at block 910, configuration compiler 808 moves the current scope up one level in the design hierarchy (block 912). The process then passes through page connector A to block 901, which depicts configuration compiler 808 moving to the next portion of the signal or configuration entity reference (i.e., the portion following the next “.”). The process thereafter returns to block 906, which has been described.

Referring now to block 920, in response to a determination that the portion of the signal or configuration entity reference under consideration does not contain a “move up” character (e.g., a “!”), configuration compiler 808 determines whether or not the design entity referenced by the portion of the signal or configuration entity reference exists in the current simulation model. If not, the process passes through page connector B to block 930 of FIG. 9B, which is described below. If, however, configuration compiler 808 determines at block 920 that the referenced design entity exists in the simulation model, configuration compiler 808 determines at block 922 whether the entity has been altered by an HDL configuration. If so, configuration compiler 808 sets an ALTER flag at block 924. From block 924 or in response to a negative determination at block 922, configuration compiler 808 moves the current scope to the indicated design entity (block 926). The process then passes through page connector A, and processing continues at block 901 and following blocks.

Referring now to block 930 of FIG. 9B, if the referenced design entity does not exist in the current simulation model, configuration compiler 808 determines whether the ALTER flag has been set for the reference under consideration. If so, the failure to resolve or bind to the referenced design entity does not necessarily represent an error condition, and the process passes to block 944, which is described below Otherwise, configuration compiler 808 flags the reference to the signal or Dial name as an error (block 932) and terminates processing of the statement at block 950.

Referring now to block 940 of FIG. 9B, configuration compiler 808 determines whether or not the signal or Dial name referenced by the statement exists within the current scope. If so, configuration compiler 808 logically binds the referenced instance of a signal or configuration entity to the Dial parameters in configuration database 814 (block 942). For example, if the reference is a signal reference, configuration compiler 808 creates in configuration database 814 a latch data structure 1204 for the configuration latch that sources the referenced signal and an output pointer 1238 in the appropriate DIDS 1202 pointing to the latch data structure 1204. Thereafter, processing of the statement by configuration compiler 808 ends at block 950.

If, however, configuration compiler 808 determines at block 940 that the referenced signal or configuration entity instance does not bind (i.e., is not present in the simulation model), configuration compiler 808 determines at block 944 if the REF flag is set. If not, an error condition has occurred, and the process passes through page connector C to blocks 932 and 950, which have been described. If, however, configuration compiler 808 determines that the REF flag is set, meaning that a failure to bind is not an error for this reference, the process passes to block 946. Block 946 depicts configuration compiler 808 indicating the failure to bind by setting a corresponding output pointer 1238 (e.g., output pointer 1238 a) in output pointer array 1236 of the appropriate DIDS 1202 to a predetermined NULL value (e.g., all ones or all zeros). Following block 946, the process terminates at block 950.

Once a configuration database 814 is constructed, the contents of configuration database 814 can be loaded into volatile memory, such as system memory 18 of data processing system 8 of FIG. 1, in order to appropriately configure a simulation model for simulation. In general, data structures 1200, 1202, 1204 and 1206 can be loaded directly into system memory 18, and may optionally be augmented with additional fields, as described below. However, as noted above, if it is desirable for the non-volatile image of configuration database 814 to be compact, it is helpful to generate additional data structures, such as Dial pointer array 1208, latch pointer array 1210 and instance pointer arrays 1226, in the volatile configuration database image in system memory 18. A process for expanding configuration database 814 within volatile memory is described, for example, in of U.S. patent application Ser. No. 10/902,628.

With the configuration database loaded into volatile memory, a simulation model can be configured and utilized to simulate a digital design through the execution of simulation software. With reference to FIG. 10, there is illustrated a block diagram depicting the contents of system memory 18 (FIG. 1) during a simulation run of a simulation model. As shown, system memory 18 includes a simulation model 1400, which is a logical representation of the digital design to be simulated, as well as software including configuration APIs 1406, a simulator 1410 and an RTX (Run Time eXecutive) 1420.

Simulator 1410 loads simulation models, such as simulation model 1400, into system memory 18. During a simulation run, simulator 1410 resets, clocks and evaluates simulation model 1400 via various APIs 1416. In addition, simulator 1410 reads values in simulation model 1400 utilizing GETFAC API 1412 and writes values to simulation model 1400 utilizing PUTFAC API 1414. Although simulator 1410 is implemented in FIG. 10 entirely in software, it will be appreciated in what follows that the simulator can alternatively be implemented at least partially in hardware.

Configuration APIs 1406 comprise software, typically written in a high level language such as C or C++, that support the configuration of simulation model 1400. These APIs, which are dynamically loaded by simulator 1410 as needed, include a first API that loads configuration model 814 from non-volatile storage and expands it in the manner described above with reference to FIG. 13 to provide a memory image of configuration database 1404. Configuration APIs 1406 further include additional APIs to access and manipulate configuration database 1404, as described in detail below.

RTX 1420 controls simulation of simulation models, such as simulation model 1400. For example, RTX 1420 loads test cases to apply to simulation model 1400. In addition, RTX 1420 delivers a set of API calls to configuration APIs 1406 and the APIs provided by simulator 1410 to initialize, configure, and simulate operation of simulation model 1400. During and after simulation, RTX 1420 also calls configuration APIs 1406 and the APIs provided by simulator 1410 to check for the correctness of simulation model 1400 by accessing various Dials, configuration latches, counters and other entities within simulation model 1400.

RTX 1420 has two modes by which it accesses Dials instantiated within simulation model 1400: interactive mode and batch mode. In interactive mode, RTX 1420 calls a first set of APIs to read from or write to one or more instances of a particular Dial within configuration database 1404. The latch value(s) obtained by reference to configuration database 1404 take immediate effect in simulation model 1400. In batch mode, RTX 1420 calls a different second set of APIs to read or write instantiations of multiple Dials in configuration database 1404 and then make any changes to simulation model 1400 at the same time.

In either interactive or batch mode, RTX 1420 must employ some syntax in its API calls to specify which Dial or Dial group instances within simulation model 1400 are to be accessed. Although a number of different syntaxes can be employed, including conventional regular expressions employing wildcarding, in an illustrative embodiment the syntax utilized to specify Dial or Dial group instances in API calls is similar to the compact expression hereinbefore described. A key difference between the compact expressions discussed above and the syntax utilized to specify Dial or Dial group instances in the RTX API calls is that, in the illustrative embodiment, Dial and Dial group instances are specified in the RTX API calls by reference to the top-level design entity of simulation model 1400 rather than relative to the design entity in which the Dial or Dial group is specified.

In the illustrative embodiment, each RTX API call targeting one or more Dial or Dial group instances in simulation model 1400 specifies the Dial or Dial group instances utilizing two parameters: an instance qualifier and a dialname qualifier. To refer to only a single Dial or Dial group instantiation, the instance qualifier takes the form “a.b.c.d”, which is the hierarchical instantiation identifier of the design entity in which the single Dial or Dial group instantiation occurs. To refer to multiple Dial or Dial group instances, the instance qualifier takes the form “a.b.c.[X]”, which identifies all instantiations of entity X within the scope of entity instance a.b.c. In the degenerate form, the instance qualifier may simply be “[X]”, which identifies all instantiations of entity X anywhere within simulation model 1400.

The dialname qualifier preferably takes the form “Entity.dialname”, where “Entity” is the design entity in which the Dial or Dial group is instantiated and “dialname” is the name assigned to the Dial or Dial group in its configuration specification statement. If bracketed syntax is employed to specify the instance qualifier, the “Entity” field can be dropped from the dialname qualifier since it will match the bracketed entity name.

Referring now to FIG. 11 there is depicted a high level logical flowchart of an exemplary process by which configuration APIs 1406 locate particular Dial or Dial group instances in configuration database 1404 based upon an instance qualifier and dialname qualifier pair in accordance with the present invention. As shown, the process begins at block 1500 in response to receipt by a configuration API 1406 of an API call from RTX 1420 containing an instance qualifier and a dialname qualifier as discussed above. In response to the API call, the configuration API 1406 enters configuration database 1404 at Dial pointer array 1208, as depicted at block 1502, and utilizes Dial pointers 1252 to locate a DDDS 1200 having a name field 1222 that exactly matches the specified dialname qualifier, as illustrated at block 1504.

Next, at block 1506, the configuration API 1406 determines whether the instance qualifier employs bracketed syntax, as described above. If so, the process passes to block 1520, which is described below. However, if the instance qualifier does not employ bracketed syntax, the configuration API 1406 follows the instance pointers 1228 of the matching DDDS 1200 to locate the single DIDS 1202 having an instance name field 1234 that exactly matches the specified instance qualifier. As indicated at blocks 1510-1512, if no match is found, the process terminates with an error. However, if a matching DIDS 1202 is located, a temporary “result” pointer identifying the single matching DIDS 1202 is created at block 1524. The process thereafter terminates at block 1526.

Returning to block 1520, if bracketed syntax is employed, the configuration API 1406 utilizes instance pointers 1228 of the matching DDDS 1200 to locate one or more DIDSs 1202 of Dial or Dial group instances within the scope specified by the prefix portion of the instance identifier preceding the bracketing. That is, a DIDS 1202 is said to “match” if the instance name field 1234 of the DIDS 1202 contains the prefix portion of the instance qualifier. Again, if no match is found, the process passes through block 1522 and terminates with an error at block 1512. However, if one or more DIDSs 1202 “match” the instance qualifier, temporary result pointers identifying the matching DIDSs 1202 are constructed at block 1524. The process shown in FIG. 11 thereafter terminates at block 1526.

With reference now to FIG. 12A, there is illustrated a high level logical flowchart of an exemplary process by which RTX 1420 reads a value of one or more Dial instances in interactive mode, in accordance with the present invention. As shown, the process begins at block 1600 in response to receipt by a configuration API 1406 of a read_Dial( ) API call by RTX 1420. As indicated at block 1602, a configuration API 1406 responds to the read_Dial( ) API call by locating within configuration database 1404 one or more DIDSs 1202 of Dial instances responsive to the API call utilizing the process described above with reference to FIG. 11.

The process then enters a loop at block 1604 in which each of the temporary result pointers generated by the process of FIG. 11 is processed. If all of the result pointers returned by the process of FIG. 11 have been processed, the process passes to block 1640, which is described below. If not, the process proceeds from block 1604 to block 1606, which illustrates the configuration API 1406 selecting a next result pointer to be processed. Next, at block 1608, the configuration API 1406 determines by reference to type field 1220 of the DDDS 1200 associated with the DIDS 1202 identified by the current result pointer whether the DIDS 1202 corresponds to a Dial group. If so, the process illustrated in FIG. 12A terminates with an error condition at block 1610 indicating that RTX 1420 has utilized the wrong API call to read a Dial instance.

In response to a determination at block 1608 that the DIDS 1202 identified by the current result pointer does not correspond to a Dial group instance, the process proceeds to block 1620. Block 1620 depicts configuration API 1406 utilizing output pointers 1238 of the DIDS 1202 (and those of any lower-level DIDS 1202 in the Dial tree) to build a data set containing the latch names from the latch name fields 1244 of latch data structures 1204 corresponding to all configuration latches ultimately controlled by the Dial instance specified in the API call. Of course, any NULL output pointers 1238 are simply skipped over when building the data set of latch names as NULL pointers do not ultimately bind to configuration latches in the simulation model. Next, as depicted at block 1622, the configuration API 1406 makes one or more API calls to GETFA.C( ) API 1412 of simulator 1410 to obtain from simulation model 1400 the latch values of all of the configuration latches listed in the data set constructed at block 1620.

Configuration API 1406 then verifies the latch values obtained from simulation model 1400 by reference to configuration database 1404, as shown at block 1624. In order to verify the latch values, configuration API 1406 utilizes mapping tables 1224 to propagate the latch values up the Dial tree from the corresponding latch data structures through intermediate DIDSs 1202, if any, until an input value for the requested Dial instance is determined. If at any point in this verification process, a Dial instance's output value generated by the verification process does not correspond to one of the legal values enumerated in its mapping table 1224, an error is detected at block 1626. Accordingly, the latch values read from simulation model 1400 and an error indication are placed in a result data structure, as illustrated at block 1630. If no error is detected, the Dial input value generated by the verification process and a success indication are placed in the result data structure, as shown at block 1628.

It will be appreciated that in some cases, the existence of one or more NULL pointers within output pointer array 1236 can leave the Dial input value corresponding to the latch values read from simulation model 1400 indeterminate in that the latch values correspond to a set of possible Dial input values rather than to a single Dial input value. In such cases, it is preferable that the set of possible Dial input values is returned with a success indication at block 1628.

As indicated by the process returning to block 1604, the above-described process is repeated for each temporary result pointer returned by the process of FIG. 11. Once all result pointers have been processed, the process passes from block 1604 to blocks 1640-1642, which illustrate the configuration API 1406 returning the result data structure to RTX 1420 and then terminating.

RTX 1420 reads Dial instances in interactive mode utilizing the method of FIG. 12A, for example, to initialize checkers that monitor portions of simulation model 1400 during simulation runs. The Dial settings of interest include not only those of top-level Dial instances, but also those of lower-level Dial instances affiliated with the portions of the simulation model 1400 monitored by the checkers.

Referring now to FIG. 12B, there is illustrated a high level logical flowchart of an exemplary process by which RTX 1420 reads a value of one or more Dial group instances in interactive mode, in accordance with the present invention. As can be seen by comparison of FIGS. 16A and 16B, the process of reading a Dial group instance is similar to the process of reading a Dial instance, but returns the value of one or more top-level Dial instances of possibly different Dial entities rather than one or more instances of the same Dial entity.

As shown, the process shown in FIG. 12B begins at block 1650 in response to receipt by a configuration API 1406 of a read_Dial_group( ) API call by RTX 1420. As indicated at block 1652, a configuration API 1406 responds to the read_Dial_group( ) API call by locating within configuration database 1404 one or more DIDSs 1202 of Dial group instances responsive to the API call utilizing the process described above with reference to FIG. 11.

The process then enters a loop at block 1654 in which each of the temporary result pointers generated by the process of FIG. 11 is processed. If all of the result pointers returned by the process of FIG. 11 have been processed, the process passes to block 1680, which is described below. If not, the process proceeds from block 1654 to block 1656, which illustrates the configuration API 1406 selecting a next result pointer to be processed. Next, at block 1658, the configuration API 1406 identifies and creates temporary pointers to all of the top-level Dial instances belonging to the Dial group instance corresponding to the DIDS 1202 referenced by the current result pointer. The top-level Dial instances are identified by locating the highest-level DIDS 1202 for each output pointer 1238 for which the type field 1220 in the associated DDDS 1220 specifies a type other than Dial group. In other words, the configuration API 1406 may have to search down through one or more hierarchical Dial groups to locate the relevant top-level Dial instances. In constructing the temporary pointers, any NULL output pointers 1238 are skipped.

The process illustrated in FIG. 12B then enters a loop beginning at block 1659 in which each of the top-level Dial instances belonging to the Dial group corresponding to the Dial group DIDS 1202 referenced by the current result pointer is individually processed to obtain the value(s) of the top-level Dial instance(s). The process next proceeds to block 1660, which depicts configuration API 1406 utilizing output pointers 1238 of the DIDS 1202 of the first (or next) top-level Dial instance (and those of any lower-level DIDS 1202 in the Dial tree) to build a data set containing the latch names from the latch name fields 1244 of latch data structures 1204 corresponding to all configuration latches ultimately controlled by the top-level Dial instance. As noted above with reference to FIG. 12A, any NULL output pointers 1238 are simply skipped over when building the data set of latch names as NULL pointers do not ultimately bind to configuration latches in the simulation model. Next, as depicted at block 1662, the configuration API 1406 makes one or more API calls to GETFAC( ) API 1412 of simulator 1410 to obtain from simulation model 1400 the latch values of all of the configuration latches listed in the data set constructed at block 1660.

At block 1664, configuration API 1406 then verifies the latch values obtained from simulation model 1400 by reference to configuration database 1404, utilizing the same technique described above with reference to block 1624 of FIG. 12A. If at any point in this verification process, a Dial instance's output value generated by the verification process does not correspond to one of the legal values enumerated in its mapping table 1224, an error is detected at block 1666. Accordingly, the latch values read from simulation model 1400 and an error indication are placed in a result data structure, as illustrated at block 1670. If no error is detected, the Dial input value generated by the verification process and a success indication are placed in the result data structure, as shown at block 1668.

It will be appreciated that in some cases, the existence of one or more NULL pointers within output pointer array 1236 can leave one or more top-level Dial input values corresponding to the latch values read from simulation model 1400 indeterminate in that the latch values correspond to a set of possible top-level Dial input values for at least one top-level Dial instance rather than to a respective, specific Dial input value for each top-level Dial instance. In such cases, it is preferable that the set of possible Dial input values for each affected top-level Dial instance is returned with a success indication at block 1668.

Following either block 1668 or block 1670, the process returns to block 1659, which represents a determination of whether or not all top-level Dials belonging to the Dial group corresponding to the DIDS 1202 referenced by the current result pointer have been processed. If not, the process returns to block 1660, which has been described. However, if all top-level Dials have been processed, the process returns to block 1654, which illustrates a determination of whether or not all result pointers have been processed. If not, the next result pointer is processed at block 1656 and following blocks, which have been described. If, however, all result pointers have been processed, the process passes to block 1680-1682, which illustrates the configuration API 1406 returning the result data structure to RTX 1420 and then terminating.

Reading Dial and Dial group instances in a batch mode of RTX 1420 is preferably handled by configuration APIs 1406 in the same manner as interactive mode, with one exception. Whereas in interactive mode latch values are always read from simulation model 1440 via calls to GETFAC( ) API 1412 at blocks 1622 and 1662, in batch mode a latch value is preferably obtained from latch value field 1246 of a latch data structure 1204 in configuration database 1404 if latch set field 1248 indicates that the corresponding configuration latch has been set. If the configuration latch has not been set, the latch value is obtained from simulation model 1440 by a call to GETFAC( ) API 1412. This difference ensures that Dial settings made in batch mode, which may not yet have been reflected in simulation model 1400, are correctly reported.

With reference now to FIG. 13A, there is illustrated a high level logical flowchart of an exemplary process by which an RTX sets a Dial instance in an interactive mode in accordance with the present invention. The process begins at block 1700 in response to receipt by a configuration API 1406 of a set_Dial( ) API call from RTX 1420. In response to the set_Dial( ) API call, the configuration API 1406 first locates and generates temporary result pointers pointing to the DIDS 1202 of the Dial instance(s) specified in the set_Dial( ) API call utilizing the technique described above with reference to FIG. 11, as illustrated at block 1702. Next, the configuration API 1406 determines at block 1704 whether or not all of the temporary result pointers point to DIDSs 1202 of top-level Dial instances. This determination can be made, for example, by examining the parent pointer 1233 of each such DIDS 1202 (and that of any higher level DIDS 1202 linked by a parent pointer 1233) and the type fields 1220 of the associated DDDSs 1200. The DIDS 1202 of a top-level Dial instance will have either a NULL parent pointer 1233 or a non-NULL parent pointer 1233 pointing to another DIDS 1202 that the type field 1220 of the associated DDDS 1200 indicates represents a Dial group. If any of the DIDSs 1202 referenced by the result pointers does not correspond to a top-level Dial instance, the process terminates at block 1708 with an error condition.

In response to a determination at block 1704 that all of the DIDSs 1202 referenced by the result pointers correspond to top-level Dial instances, a further determination is made at block 1706 whether or not the specified value to which the Dial instance(s) are to be set is one of the values specified in the mapping table 1224 of the associated DDDS 1200. If not, the process terminates with an error at block 1708. However, in response to a determination at block 1706 that the specified value to which the Dial instance(s) are to be set is one of the legal values, the process enters a loop including blocks 1710-1716 in which each result pointer is processed to set a respective Dial instance.

At block 1710, configuration API 1406 determines whether or not all result pointers have been processed. If so, the process terminates at block 1720. If, however, additional result pointers remain to be processed, the next result pointer to be processed is selected at block 1712. Next, at block 1714, configuration API 1406 propagates the Dial setting specified in the set_Dial( ) API call down the Dial tree headed by the top-level Dial instance associated with the DIDS 1202 referenced by the current result pointer. In order to propagate the desired Dial setting, mapping table 1224 in the DDDS 1200 associated with the DIDS 1202 referenced by the current result pointer is first referenced, if necessary, (i.e., for CDials and LDials) to determine the output values for each of output pointers 1238 in the output pointer array 1236 of the DIDS 1202 referenced by the current result pointer. These output values are propagated down the Dial tree as the input values of the next lower-level Dial instances, if any, corresponding to the DIDSs 1202 referenced by output pointers 1238. This propagation continues until a latch value is determined for each configuration latch terminating the Dial tree (which are represented in configuration database 1404 by latch data structures 1204). NULL output pointers 1238, if any, are simply skipped over as the output values are propagated down the Dial tree.

As shown at block 1716, as each latch value for a configuration latch is determined, the configuration API 1406 makes a call to PUTFAC( ) API 1414 to set the configuration latch in simulation model 1400 to the determined value utilizing the latch name specified within the latch name field 1244 of the corresponding latch data structure 1204. Thereafter, the process returns to block 1710, which represents the processing of the top-level Dial corresponding to the next result pointer. After all result pointers are processed, the process terminates at block 1720.

Referring now to FIG. 13B, there is depicted a high level logical flowchart of an illustrative process by which an RTX sets a Dial group in an interactive mode in accordance with the present invention. The process begins at block 1730 in response to receipt by a configuration API 1406 of a set_Dial_group( ) API call from an RTX 1420. In response to the set_Dial_group( ) API call, the configuration API 1406 first locates and generates temporary result pointers pointing to the DIDS 1202 of the Dial group instance(s) specified in the set_Dial_group( ) API call utilizing the technique described above with reference to FIG. 11, as depicted at block 1732. Next, the configuration API 1406 determines at block 1734 whether or not all of the temporary result pointers point to DIDSs 1202 of top-level Dial group instances. This determination can be made, for example, by examining the parent pointer 1233 of each such DIDS 1202 to ascertain whether the parent pointer 1233 is NULL. If any of the DIDSs 1202 referenced by the result pointers does not correspond to a top-level Dial group (i.e., has a non-NULL parent pointer 1233), the process terminates at block 1736 with an error condition.

In response to a determination at block 1734 that each of the DIDSs 1202 referenced by the result pointers corresponds to a top-level Dial group, the process passes to blocks 1738-1740. Block 1738 illustrates configuration API 1406 locating all of the top-level Dial instances within each Dial group for which the corresponding DIDS 1202 is referenced by a result pointer. Then, as depicted at block 1740, the configuration API 1406 determines whether or not the specified value to which each top-level Dial instance is to be set is one of the values specified in the mapping table 1224 of the corresponding DDDS 1200. If not, the process terminates with an error at block 1736.

In the illustrated embodiment, the prevalidation steps illustrated at blocks 1734, 1738 and 1740 are performed prior to setting any Dial instances because it is deemed preferable to implement setting a Dial group instance as an atomic operation that either successfully sets all relevant top-level Dial instances or completely fails. In this manner, a complex condition in which some top-level Dial instances within the Dial group instance are set and others are not can be avoided.

In response to a determination at block 1740 that the specified value to which each top-level Dial instance is to be set is one of the legal values, the process enters a loop including blocks 1750-1756 in which each result pointer is processed to set the top-level Dial instance(s) belonging to each Dial group instance.

At block 1750, the configuration API 1406 determines whether or not all result pointers have been processed. If so, the process terminates at block 1760. If, however, additional result pointers remain to be processed, the next result pointer to be processed is selected at block 1752. Next, at block 1754, configuration API 1406 propagates the Dial setting specified for each top-level Dial in the set_Dial_group( ) API call down the Dial trees of the top-level Dial instances belonging to the Dial group instance corresponding to the DIDS 1202 referenced by the current result pointer. The propagation of Dial settings down the Dial trees is performed in the same manner discussed above with reference to block 1714 of FIG. 13A. As shown at block 1756, as each latch value for a configuration latch is determined, the configuration API 1406 makes a call to PUTFAC( ) API 1414 to set the configuration latch in simulation model 1400 to the determined value utilizing the latch name specified within the latch name field 1244 of the corresponding latch data structure 1204. Thereafter, the process returns to block 1750, which represents the processing of the top-level Dial corresponding to the next result pointer, if any.

With reference now to FIG. 14A, there is illustrated a high level logical flowchart of an exemplary method of setting Dial and Dial group instances in batch mode in accordance with the present invention. As illustrated, the process begins at block 1800 and thereafter proceeds to block 1802, which illustrates RTX 1420 initializing configuration database 1404 by calling a configuration API 1406 (e.g., start_batch( )) in order to initialize configuration database 1404. The start_batch( ) API routine initializes configuration database 1404, for example, by setting each instance set field 1239, latch set field 1248, and set history field 1249 in configuration database 1404 to FALSE. By resetting all of the “set” fields in configuration database 1404, the Dials and configuration latches that are not set by the current batch mode call sequence can be easily detected, as discussed below.

Following initialization of configuration database 1404 at block 1802, the process shown in FIG. 14A proceeds to block 1804. Block 1804 illustrates RTX 1420 optionally issuing one or more read_Dial( ) or read_Dial_group( ) API calls to read one or more Dials or Dial groups as discussed above with respect to FIGS. 12A and 12B, and optionally issuing one or more batch mode set_Dial( ) or set_Dial_group( ) API calls to enter settings for Dial instances and their underlying configuration latches into configuration database 1404. A configuration API 1406 responds to the “set” API calls in the same manner described above with respect to FIG. 13A (for setting Dial instances) or FIG. 13B (for setting Dial group instances), with two exceptions. First, when any top-level or lower-level Dial instances are set, whether as a result of a set_Dial( ) or set_Dial_group( ) API call, the instance set field 1239 of the corresponding DIDS 1202 is set to TRUE. Second, no latch values are written to simulation model 1400 by the “set” API routines, as illustrated at blocks 1716 and 1756 of FIGS. 13A-13B. Instead, the latch values are written into latch value fields 1246 of the latch data structure 1204 corresponding to each affected configuration latch, and the latch set field 1248 is updated to TRUE. In this manner, the Dial instances and configuration latches that are explicitly set by the API call can be readily identified during subsequent processing.

Following block 1804, the process passes to block 1806, which illustrates RTX 1420 calling an end_batch( ) API routine among configuration APIs 1406 to complete the present phase of default application. As indicated at block 1806 and as described in detail below with respect to FIG. 14B, the end_batch( ) API routine applies selected default values, if any, to specified Dial instances and propagates these default values to underlying configuration latches into configuration database 1404. The latch values of all configuration latches set explicitly or with a default value are then potentially applied to latches within the simulation model. Finally, preparation is made for a next phase, if any.

If RTX 1420 has an additional phase of default application, the process passes from block 1806 to block 1808 and then returns to block 1804, which represents RTX 1420 initiating a next phase of default application. If, however, all phases of default application have been processed, the process illustrated in FIG. 14A passes from block 1806 through block 1808 to block 1810, where the batch process terminates.

Referring now to FIG. 14B, there is depicted a high level logical flowchart of an exemplary embodiment of the end_phase( ) API routine called at block 1806 of FIG. 14A. As shown, the process begins at block 1820 when the end_phase( ) API routine is called by RTX 1420, for example, with the following statement:

End_phase(phases, unnamed, instance_qualifier, apply)

In this exemplary API call, the “phases” parameter is a string specifying the phase ID(s) of defaults to be applied at the end of the current phase; “unnamed” is a Boolean parameter indicating whether or not defaults values without any associated phase ID should be applied during the current phase; “apply” is a Boolean-valued parameter indicating whether or not configuration latch values should be immediately applied to simulation model 1400; and “instance_qualifier” is one or more regular expressions that can be utilized to limit which instances of a particular Dial are processed to apply defaults.

By specifying an instance_qualifier parameter for the end_phase( ) API routine, a user can limit the application of defaults to only a portion of simulation model 1400. The ability to restrict the application of defaults in this manner is particularly useful in cases in which two sections of the simulation model 1400 (e.g., sections representing two different integrated circuit chips) have different phasing requirements but use the same phase IDs. Thus, collisions in phase IDs can be resolved by appropriate specification of the instance_qualifier used in conjunction with the phase ID.

The end_phase( ) API routine then enters a processing loop including blocks 1822-1838 in which DIDSs 1202 within configuration database 1404 are processed to apply appropriate Dial default values, if any. Referring first to block 1822, the end_phase( ) API determines whether or not all top-level pointers 1250 within top-level pointer array 1206 have been processed. If so, the process proceeds from block 1822 to block 1840, which is described below. If not all top-level pointers 1250 within top-level pointer array 1206 have been processed, the process proceeds to block 1824. Block 1824 represents the end_phase( ) API routine recursively scanning the DIDSs 1202 pointed to by a next top-level pointer 1250 and its descendant DIDSs 1202, if any, to apply the default values indicated by the parameters of the end_phase( ) API call. If the end_phase( ) API routine determines at block 1826 that it has processed all necessary DIDSs 1202 in the subtree of the top-level DIDS 1202 identified by the current top-level pointer 1250, then the process returns to block 1822, which has been described. If, however, at least one DIDS 1202 in the subtree of the top-level DIDS 1202 identified by the current top-level pointer 1250 remains to be processed, the process passes from block 1826 to block 1828.

Block 1828 illustrates the end_phase( ) API routine examining a next DIDS 1202 to determine whether or not its default field 1229 has a non-NULL value. If the current DIDS 1202 does not contain a non-NULL default field 1229, the process returns to block 1824, representing the end_phase API routine continuing the recursive processing of DIDSs 1202 in the subtree of the top-level DIDS 1202 pointed to by the current top-level pointer 1250. If the default field 1229 contains a non-NULL value, the process passes to block 1830, which depicts a determination of whether or not the instance set field 1239 is set, that is, whether the Dial instance was previously explicitly set at block 1804 of FIG. 14A. If the instance set field 1239 is set, the default value contained in default field 1229 is ignored (since the simulation user has already explicitly specified a value for the associated Dial instance). And because simulation database 1400 is constructed so that any descendant of a DIDS 1202 having a specified default cannot have a default value, the process passes to block 1836, which illustrates the end_phase( ) API routine skipping the processing of any DIDS 1202 in the subtree of the current DIDS 1202. Thereafter, the process returns to block 1824, which has been described.

Returning to block 1830, in response to a determination that the instance set field 1239 of the current DIDS 1202 is not set, the process proceeds to block 1832. Block 1832 illustrates end_phase( ) API interrogating phase ID field 1227 of the current DIDS 1202 to determine whether the default value stored in default field 1229 has one or more associated phase IDs. If not, the process passes to block 1833, which is described below. In response to a determination at block 1832 that phase ID field 1227 stores at least one phase ID, the end_phase( ) API next determines at block 1834 whether the phases parameter of the end_phase( ) API call specifies a phase ID that matches a phase ID contained within phase ID field 1227. If no match is found, the process passes from block 1834 to block 1836, which has been described. If, on the other hand, a phase ID specified in the phases parameter of the end_phase( ) API call matches a phase ID contained within the phase ID field 1227 of the current DIDS 1202, the end_phase( ) API next determines at block 1835 whether or not the Dial instance name contained in instance name field 1234 of the current DIDS 1202 matches the qualifying expression passed as the instance_qualifier parameter of the end_phase( ) API call. Again, in response to a negative determination at block 1835, the process passes to block 1836, which has been described. If, on the other hand, the Dial instance name contained within instance name field 1234 is qualified by the instance_qualifier parameter, the process proceeds to block 1838, which is described below.

Returning to block 1833, if the current DIDS 1202 does not have one or more phase IDs specified within phase ID field 1227, a further determination is made whether or not the unnamed parameter of the end_phase( ) API call has a value of TRUE to indicate the default values without any associated phase information should be applied during the current phase. If not, the process passes from block 1833 to block 1836, which has been described. If, on the other hand, the end_phase( ) API determines at block 1833 that defaults without associated phase information should be applied during the current phase, the process proceeds to block 1835, which has been described above.

Thus, when the end_phase( ) API reaches block 1838, end_phase( ) API has, by the determinations illustrated at 1830, 1832, 1833, 1834 and 1835 determined that the default specified for the Dial instance corresponding to the current DIDS 1202 should be applied in the current phase of batch mode execution. Accordingly, at block 1838, the end_phase( ) API routine applies the default value specified in the default field 1229 to mapping table 1224 to generate one or more Dial output signal(s), which are then propagated down the Dial tree of the current DIDS 1202 in the manner hereinbefore described. Ultimately, the latch value fields 1246 and latch set field 1248 of each of the underlying latch data structures 1204 within configuration database 1404 are set to values corresponding to the Dial default value. The process then proceeds from block 1838 to block 1836, which has been described.

Returning to block 1822, in response to a determination that the Dial trees of all of the DIDS 1202 pointed to by top-level pointers 1250 have been processed to apply any appropriate default values in the manner described above, the process next passes to block 1840. Block 1840 depicts end_phase( ) API examining the apply parameter of the end_phase( ) API call to determine whether or not the configuration latch values within latch data structures 1204 should be applied to simulation model 1400. The added degree of control represented by this determination is advantageous in that different sections of simulation model 1400, which may have colliding phase IDs, can be independently configured within configuration database 1404 in different phases, but the resulting configuration latch values can be applied to simulation model 1400 at the same time, if desired. If the apply parameter has the value FALSE, meaning that the configuration latch values are not to be applied to simulation model 1400 during the current phase, the process passes directly to block 1844.

If, however, configuration latch values are to be applied to simulation model 1400 during the current phase, as indicated by an apply parameter value of TRUE, the end_phase( ) API routine proceeds to block 1842. At block 1842, the end_phase( ) API utilizes latch pointer array 1210 to examine each latch data structure 1204 in configuration database 1404. For each latch data structure 1204 in which latch set field 1248 has the value TRUE, the end_batch( ) API routine issues a call to PUTFAC( ) API 1414 of simulator 1410 to update simulation model 1400 with the latch value contained in latch value field 1246. In addition, as shown at block 1844, the end_phase( ) API performs a logical OR operation between the value of latch set field 1248 and set history field 1249, storing the result within set history field 1249. In this manner, each set history field 1249 maintains an indication of whether or not the corresponding configuration latch has been set during any phase of the batch mode process.

Following block 1844, the end_batch API proceeds to block 1846, which depicts the end_batch API routine resetting all of Dial set fields 1239 in DIDS 1202 and all latch set fields 1248 in preparation of a next phase, if any. Thereafter, the end_phase API routine terminates at block 1848.

In summary, the end_phase( ) API routine applies Dial default values to configuration database 1404 that match the limiting phase and instance_qualifiers and then optionally applies the resulting configuration latch values to simulation model 1400 in accordance with the apply parameter. Finally, the end_phase( ) API routine tracks which latch data structures 1204 have been set utilizing set history fields 1249, and resets various set fields to prepare for a next phase, if any.

As has been described, in at least one embodiment, one or more hardware description language (HDL) files are utilized to describe a plurality of hierarchically arranged design entities defining a digital design to be simulated and a plurality of configuration entities not belonging to the digital design that logically control settings of a plurality of configuration latches in the digital design. The HDL file(s) are compiled to obtain a simulation executable model of the digital design and an associated configuration database. The compiling includes parsing a configuration statement that specifies an association between an instance of a configuration entity and a specified configuration latch, determining whether or not the specified configuration latch is described in the HDL file(s), and if not, creating an indication in the configuration database that the instance of the configuration latch had a specified association to a configuration latch to which it failed to bind.

While the invention has been particularly shown as described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention. For example, it will be appreciated that the concepts disclosed herein may be extended or modified to apply to other types of configuration entities than those disclosed herein. In addition, those skilled in the understand upon reference to the foregoing that any of a wide variety of rules may be applied to determine which configuration entities are presented, meaning that the particular syntax and presentation rules described herein are merely exemplary and not exhaustive.

Furthermore, although aspects of the present invention have been described with respect to a computer system executing software that directs the functions of the present invention, it should be understood that present invention may alternatively be implemented as a program product for use with a data processing system. Program code defining the functions of the present invention can be delivered to a data processing system via a variety of signal-bearing or computer readable storage media as is known in the art. It should be understood, therefore, that such signal-bearing or computer readable storage media, when carrying or encoding program code that direct the functions of the present invention, represent alternative embodiments of the present invention. 

1. A method of data processing, said method comprising: receiving one or more hardware description language (HDL) files describing: a plurality of hierarchically arranged design entities defining a digital design to be simulated, wherein said plurality of hierarchically arranged design entities contain a plurality of configuration latches; and a plurality of configuration entities not belonging to the digital design that logically control settings of the plurality of configuration latches; compiling the one or more HDL files to obtain a simulation executable model of the digital design and an associated configuration database representing the plurality of configuration entities and instances thereof, wherein the compiling includes: parsing a configuration statement that specifies an association between an instance of a configuration entity among the plurality of configuration entities and a specified configuration latch; determining whether or not the specified configuration latch is described in the one or more HDL files; and in response to determining that the specified configuration latch is not described in the one or more HDL files, creating an indication in the configuration database that the instance of the configuration latch had a specified association to a configuration latch to which it failed to bind.
 2. The method of claim 1, wherein the indication comprises a null pointer.
 3. The method of claim 1, and further comprising: creating a data structure representing the instance of the configuration entity in the configuration database.
 4. The method of claim 1, wherein determining that the specified configuration latch is not described in the one or more HDL files comprises determining that a particular design entity containing the specified configuration latch is not included within the simulation executable model.
 5. The method of claim 1, wherein said creating comprises creating the indication in the configuration database only if the one or more HDL files indicate that the configuration statement can fail to bind without error.
 6. A program product, comprising: a computer readable storage medium; and program code stored within the computer readable storage medium, wherein the program code when processed by a computer system causes the computer system to: receive one or more hardware description language (HDL) files describing: a plurality of hierarchically arranged design entities defining a digital design to be simulated, wherein said plurality of hierarchically arranged design entities contain a plurality of configuration latches; and a plurality of configuration entities not belonging to the digital design that logically control settings of the plurality of configuration latches; compile the one or more HDL files to obtain a simulation executable model of the digital design and an associated configuration database representing the plurality of configuration entities and instances thereof, wherein the compiling includes: parsing a configuration statement that specifies an association between an instance of a configuration entity among the plurality of configuration entities and a specified configuration latch; determining whether or not the specified configuration latch is described in the one or more HDL files; and in response to determining that the specified configuration latch is not described in the one or more HDL files, creating an indication in the configuration database that the instance of the configuration latch had a specified association to a configuration latch to which it failed to bind.
 7. The program product of claim 6, wherein the indication comprises a null pointer.
 8. The program product of claim 6, wherein the program code further causes the computer system to create a data structure representing the instance of the configuration entity in the configuration database.
 9. The program product of claim 6, wherein the determination that the specified configuration latch is not described in the one or more HDL files comprises a determination that a particular design entity containing the specified configuration latch is not included within the simulation executable model.
 10. The program product of claim 6, wherein said program code causes the computer system to create the indication in the configuration database only if the one or more HDL files indicate that the configuration statement can fail to bind without error.
 11. A data processing system, comprising: a processor; data storage coupled to the processor; and program code stored within the data storage and executable by the processor, wherein the program code when processed by a computer system causes the computer system to: receive one or more hardware description language (HDL) files describing: a plurality of hierarchically arranged design entities defining a digital design to be simulated, wherein said plurality of hierarchically arranged design entities contain a plurality of configuration latches; and a plurality of configuration entities not belonging to the digital design that logically control settings of the plurality of configuration latches; compile the one or more HDL files to obtain a simulation executable model of the digital design and an associated configuration database representing the plurality of configuration entities and instances thereof, wherein the compiling includes: parsing a configuration statement that specifies an association between an instance of a configuration entity among the plurality of configuration entities and a specified configuration latch; determining whether or not the specified configuration latch is described in the one or more HDL files; and in response to determining that the specified configuration latch is not described in the one or more HDL files, creating an indication in the configuration database that the instance of the configuration latch had a specified association to a configuration latch to which it failed to bind.
 12. The data processing system of claim 11, wherein the indication comprises a null pointer.
 13. The data processing system of claim 11, wherein the program code further causes the computer system to create a data structure representing the instance of the configuration entity in the configuration database.
 14. The data processing system of claim 11, wherein the determination that the specified configuration latch is not described in the one or more HDL files comprises a determination that a particular design entity containing the specified configuration latch is not included within the simulation executable model.
 15. The data processing system of claim 11, wherein said program code causes the computer system to create the indication in the configuration database only if the one or more HDL files indicate that the configuration statement can fail to bind without error. 